User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 12: Optional Features 12–3
ECRC
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Table 12–1 summarizes the RX ECRC functionality for all possible conditions.
ECRC on the TX Path
When the ECRC generation option is on, the TX path generates ECRC. If you turn on
ECRC forwarding, the ECRC value is forwarded with the TLP. Table 12–2
summarizes the TX ECRC generation and forwarding. In this table, if
TD
is 1, the TLP
includes an ECRC.
TD
is the TL digest bit of the TL packet described in Appendix A,
Transaction Layer Packet (TLP) Header Formats.
Table 12–1. ECRC Operation on RX Path
ECRC
Forwarding
ECRC
Check
Enable
(1)
ECRC
Status
Error TLP Forward to Application Layer
No
No
none No Forwarded
good No Forwarded without its ECRC
bad No Forwarded without its ECRC
Yes
none No Forwarded
good No Forwarded without its ECRC
bad Yes Not forwarded
Yes
No
none No Forwarded
good No Forwarded with its ECRC
bad No Forwarded with its ECRC
Yes
none No Forwarded
good No Forwarded with its ECRC
bad Yes Not forwarded
Note to Table 12–1:
(1) The
ECRC Check Enable
is in the
Configuration Space Advanced Error Capabilities and Control
Register.
Table 12–2. ECRC Generation and Forwarding on TX Path
(1)
ECRC
Forwarding
ECRC
Generation
Enable
(2)
TLP on Application
Layer
TLP on Link Comments
No
No
TD
=0, without ECRC
TD
=0, without ECRC
TD
=1, without ECRC
TD
=0, without ECRC
Yes
TD
=0, without ECRC
TD
=1, with ECRC
ECRC is generated
TD
=1, without ECRC
TD
=1, with ECRC
Yes
No
TD
=0, without ECRC
TD
=0, without ECRC
Core forwards the
ECRC
TD
=1, with ECRC
TD
=1, with ECRC
Yes
TD
=0, without ECRC
TD
=0, without ECRC
TD
=1, with ECRC
TD
=1, with ECRC
Notes to Table 12–2:
(1) All unspecified cases are unsupported and the behavior of the Hard IP is unknown.
(2) The
ECRC Generation Enable
is in the
Configuration Space Advanced Error Capabilities and
Control
Register.