User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
12–2 Chapter 12: Optional Features
ECRC
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
CvP has the following advantages:
■ Provides a simpler software model for configuration. A smart host can use the
PCIe protocol and the application topology to initialize and update the FPGA
fabric.
■ Enables dynamic core updates without requiring a system power down.
■ Improves security for the proprietary core bitstream.
■ Reduces system costs by reducing the size of the flash device to store the .pof.
■ Facilitates hardware acceleration.
■ May reduce system size because a single CvP link can be used to configure
multiple FPGAs.
1 For Gen1 variants, you cannot use dynamic transceiver reconfiguration for the
transceiver channels in the CvP-enabled Hard IP when CvP is enabled.
f For more information about CvP, refer to Configuration via Protocol (CvP)
Implementation in Altera FPGAs User Guide and Configuring FPGAs Using an
Autonomous PCIe Core and CvP.
ECRC
ECRC ensures end-to-end data integrity for systems that require high reliability. You
can specify this option under the Error Reporting heading. The ECRC function
includes the ability to check and generate ECRC. In addition, the ECRC function can
also forward the TLP with ECRC to the RX port of the Application Layer. When using
ECRC forwarding mode, the ECRC check and generate are performed in the
Application Layer.
You must turn on Advanced error reporting (AER), ECRC checking, ECRC
generation, and ECRC forwarding under the PCI Express/PCI Capabilities page of
the parameter editor to enable this functionality.
f For more information about error handling, refer to the Error Signaling and Logging
which is Section 6.2 of the PCI Express Base Specification, Rev. 2.1.
ECRC on the RX Path
When the ECRC generation option is turned on, errors are detected when receiving
TLPs with a bad ECRC. If the ECRC generation option is turned off, no error
detection occurs. If the ECRC forwarding option is turned on, the ECRC value is
forwarded to the Application Layer with the TLP. If the ECRC forwarding option is
turned off, the ECRC value is not forwarded.