User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 11: Interrupts 11–7
Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Enabling MSI or Legacy Interrupts
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts
automatically based on the standard interrupt controls in the PCI Express
Configuration Space registers. Software can write the
Interrupt Disable
bit, which is
bit 10 of the
Command
register (at Configuration Space offset 0x4) to disable legacy
interrupts. Software can write the
MSI Enable
bit, which is bit 0 of the
MSI Control
Status
register in the MSI capability register (bit 16 at configuration space offset
0x50), to enable MSI interrupts.
Software can only enable one type of interrupt at a time. However, to change the
selection of MSI or legacy interrupts during operation, software must ensure that no
interrupt request is dropped. Therefore, software must first enable the new selection
and then disable the old selection. To set up legacy interrupts, software must first
clear the
Interrupt Disable
bit and then clear the
MSI enable
bit. To set up MSI
interrupts, software must first set the
MSI enable
bit and then set the
Interrupt
Disable
bit.
Generation of Avalon-MM Interrupts
Generation of Avalon-MM interrupts requires the instantiation of the CRA slave
module where the interrupt registers and control logic are implemented. The CRA
slave port has an Avalon-MM Interrupt,
CRAIrq_o
, output signal. A write access to an
Avalon-MM mailbox register sets one of the
P2A_MAILBOX_INT
<n> bits in the “PCI
Express to Avalon-MM Interrupt Status Register for Endpoints 0x3060” on
page 8–21and asserts the, if enabled. Software can enable the interrupt by writing to
the “INT-X Interrupt Enable Register for Endpoints 0x3070” on page 8–21 through the
CRA slave. After servicing the interrupt, software must clear the appropriate serviced
interrupt
status
bit in the PCI-Express-to-Avalon-MM
Interrupt Status
register and
ensure that there is no other interrupt pending.
Interrupts for End Points Using the Avalon-MM Interface with Multiple
MSI/MSI-X Support
If you select Enable multiple MSI/MSI-X support under the Avalon-MM System
Settings banner in the GUI, the Hard IP for PCI Express exports the MSI, MSI-X, and
INTx interfaces to the Application Layer. The Application Layer must include a
Custom Interrupt Handler to send interrupts to the Root Port. You must design this
Custom Interrupt Handler. Figure 11–6 provides a an overview of the logic for the
Custom Interrupt Handler. The Custom Interrupt Handler should include hardware
to perform the following tasks:
■ An MSI/MXI-X IRQ Avalon-MM Master port to drive MSI or MSI-X interrupts as
memory writes to the PCIe Avalon-MM Bridge.
■ A legacy interrupt signal,
IntxReq_i
, to drive legacy interrupts from the
MSI/MSI-X IRQ module to the Hard IP for PCI Express.
■ An MSI/MSI-X Avalon-MM Slave port to receive interrupt control and status from
the PCIe Root Port.