User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
2–4 Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express
Customizing the Endpoint in the MegaWizard Plug-In Manager Design Flow
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
1. On the Tools menu, click MegaWizard Plug-In Manager. The MegaWizard
Plug-In Manager appears.
2. Select Create a new custom megafunction variation and click Next.
3. In Which device family will you be using? Select the Cyclone V device family.
4. Expand the Interfaces directory under Installed Plug-Ins by clicking the + icon
left of the directory name, expand PCI Express, then click Cyclone V Hard IP for
PCI Express <version_number>
5. Select the output file type for your design. This walkthrough supports VHDL and
Verilog HDL. For this example, select Verilog HDL.
6. Specify a variation name for output files <working_dir>/example_design/
<variation name>. For this walkthrough, specify <working_dir>/example_design/
gen1_x4.
7. Click Next to open the parameter editor for the Cyclone V Hard IP for PCI
Express.
8. Specify the System Settings values listed inTable 2–1.
1 Each function shares the parameter settings on the Device, Error Reporting, Link,
Slot, and Power Management tabs. Each function has separate parameter settings for
the Base Address Registers, Base and Limit Registers for Root Ports, Device
Identification Registers, and the PCI Express/PCI Capabilities parameters. When
you click on a Func<n> tab under the Port Functions heading, the tabs automatically
reflect the Func<n> tab selected.
9. Specify the Device parameters listed in Table 2–2.
Table 2–1. System Settings Parameters
Parameter Value
Number of Lanes x4
Lane Rate Gen 1 (2.5 Gbps)
Port type Native endpoint
Application Layer interface Avalon-ST 64-bit
RX buffer credit allocation - performance for
received requests
Low
Reference clock frequency 100 MHz
Use 62.5 MHz Application Layer clock for ×1 Leave this option off
Use deprecated RX Avalon-ST data byte enable
port (rx_st_be)
Leave this option off
Enable configuration via the PCIe link Leave this option off
Number of functions 1
Table 2–2. Device
Parameter Value
Maximum payload size 128 bytes
Number of tags supported 32