User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 11: Interrupts 11–5
Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
The
Root Error Status
register reports the status of error messages. The
Root Error
Status
register is part of the PCI Express AER Extended Capability structure. It is
located at offset 0x830 of the Configuration Space registers.
Interrupts for Endpoints Using the Avalon-MM Interface to the
Application Layer
The PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The completer
only single dword variant includes an interrupt generation module. For other variants
with the Avalon-MM interface, interrupt support requires instantiation of the CRA
slave module where the interrupt registers and control logic are implemented.
The PCI Express Avalon-MM bridge supports the Avalon-MM individual requests
interrupt scheme: multiple input signals indicate incoming interrupt requests, and
software must determine priorities for servicing simultaneous interrupts the
Avalon-MM Cyclone V Hard IP for PCI Express receives.
The RX master module port has as many as 16 Avalon-MM interrupt input signals
(
RXmirq_irq[
<n>
:0]
, where <n> 16)) . Each interrupt signal indicates a distinct
interrupt source. Assertion of any of these signals, or a PCI Express mailbox register
write access, sets a bit in the PCI Express interrupt status register. Multiple bits can be
set at the same time; software determines priorities for servicing simultaneous
incoming interrupt requests. Each set bit in the PCI Express interrupt status register
generates a PCI Express interrupt, if enabled, when software determines its turn.
Software can enable the individual interrupts by writing to the“INT-X Interrupt
Enable Register for Endpoints 0x3070” on page 8–21 through the CRA slave.
When any interrupt input signal is asserted, the corresponding bit is written in the
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 8–12.
Software reads this register and decides priority on servicing requested interrupts.
After servicing the interrupt, software must clear the appropriate serviced interrupt
status
bit and ensure that no other interrupts are pending. For interrupts caused by
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 8–12 mailbox
writes, the status bits should be cleared in the “Avalon-MM to PCI Express Interrupt
Status Register 0x0040” on page 8–12. For interrupts due to the incoming interrupt
signals on the Avalon-MM interface, the interrupt status should be cleared in the
Avalon-MM component that sourced the interrupt. This sequence prevents interrupt
requests from being lost during interrupt servicing.