User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
11. Interrupts
This chapter describes interrupts for the following configurations:
■ Interrupts for Endpoints Using the Avalon-ST Application Interface
■ Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
■ Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
Refer to “Interrupts for Endpoints” on page 7–27 and “Interrupts for Root Ports” on
page 7–28 for descriptions of the interrupt signals.
Interrupts for Endpoints Using the Avalon-ST Application Interface
The Cyclone V Hard IP for PCI Express provides support for PCI Express MSI, MSI-X,
and legacy interrupts when configured in Endpoint mode. The MSI, MSI-X, and
legacy interrupts are mutually exclusive. After power up, the Hard IP block starts in
INTX mode, after which time software decides whether to switch to MSI mode by
programming the
msi_enable
bit of the
MSI message control
register (bit[16] of
0x050) to 1 or to MSI-X mode if you turn on Implement MSI-X under the PCI
Express/PCI Capabilities tab using the parameter editor. If you turn on the
Implement MSI-X option, you should implement the MSI-X table structures at the
memory space pointed to by the BARs.
f Refer to section 6.1 of PCI Express 2.1 Base Specification for a general description of PCI
Express interrupt support for Endpoints.
MSI Interrupts
MSI interrupts are signaled on the PCI Express link using a single dword memory
write TLPs generated internally by the Cyclone V Hard IP for PCI Express. The
app_msi_req
input port controls MSI interrupt generation. When the input port
asserts
app_msi_req
, it causes a MSI posted write TLP to be generated based on the
MSI configuration register values and the
app_msi_tc
and
app_msi_num
input ports.
Software uses configuration requests to program the MSI registers. To enable MSI
interrupts, software must first set the
MSI
enable
bit (Table 7–15 on page 7–37) and
then disable legacy interrupts by setting the
Interrupt Disable
which is bit 10 of the
Command
register (Table 8–2 on page 8–2).
December 2013
UG-01110-1.5