User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 10: Transaction Layer Protocol (TLP) Details 10–5
Receive Buffer Reordering
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
1 MSI requests are conveyed in exactly the same manner as PCI Express memory write
requests and are indistinguishable from them in terms of flow control, ordering, and
data integrity.
Spec
(10)
Hard IP Spec Hard IP Spec Hard IP Spec Hard IP Spec Hard IP
Posted
Memory Write or
Message
Request
N
(11)
Y/N
(12)
N
(11)
N
(12)
YYYY
Y/N
(11)
Y
(12)
N
(11)
N
(12)
Y/N
(11)
Y
(12)
N
(11)
N
(12)
NonPosted
Read Request N N Y/N N
(11)
Y/N N
(12)
Y/N N Y/N N
I/O or
Configuration
Write Request
NNY/NN
(13)
Y/N N
(14)
Y/N N Y/N N
Completion
Read Completion
N
(11)
Y/N
(12)
N
(11)
N
(12)
YYYY
Y/N
(11)
N
(12)
N
(11)
N
(12)
Y/N N
I/O or
Configuration
Write
Completion
Y/NNYYYYY/NNY/NN
Notes to Table 10–2:
(1) A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not pass any other Memory Write or Message
Request.
(2) A Memory Write or Message Request with the Relaxed Ordering Attribute bit set (b’1) is permitted to pass any other Memory Write or Message
Request.
(3) Endpoints, Switches, and Root Complex may allow Memory Write and Message Requests to pass Completions or be blocked by Completions.
(4) Memory Write and Message Requests can pass Completions traveling in the PCI Express to PCI directions to avoid deadlock.
(5) If the Relaxed Ordering attribute is not set, then a Read Completion cannot pass a previously enqueued Memory Write or Message Request.
(6) If the Relaxed Ordering attribute is set, then a Read Completion is permitted to pass a previously enqueued Memory Write or Message Request.
(7) Read Completion associated with different Read Requests are allowed to be blocked by or to pass each other.
(8) Read Completions for Request (same Transaction ID) must return in address order.
(9) Non-posted requests cannot pass other non-posted requests.
(10) Refers to the PCI Express Base Specification 3.0.
(11)
CfgRd0
can pass
IORd
or
MRd
.
(12)
CfgWr0
can
IORd
or
MRd
.
(13)
CfgRd0
can pass
IORd
or
MRd
.
(14)
CfrWr0
can pass
IOWr
.
Table 10–2. Transaction Ordering Rules
(1)– (9)
(Part 2 of 2)