User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
10–2 Chapter 10: Transaction Layer Protocol (TLP) Details
Supported Message Types
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Error Signaling Messages
ERR_COR Receive Transmit No Yes No
In addition to detecting errors, a Root Port
also gathers and manages errors sent by
downstream components through the
ERR_COR, ERR_NONFATAL, AND ERR_FATAL
Error Messages. In Root Port mode, there are
two mechanisms to report an error event to
the Application Layer:
■
serr_out
output signal. When set,
indicates to the Application Layer that an
error has been logged in the AER capability
structure
■
tl_aer_msi_num
input signal. When the
Implement advanced error reporting
option is turned on, you can set
tl_aer_msi_num
to indicate which MSI is
being sent to the root complex when an
error is logged in the AER Capability
structure.
ERR_NONFATAL Receive Transmit No Yes No
ERR_FATAL Receive Transmit No Yes No
Locked Transaction Message
Unlock Message Transmit Receive Yes No No
Slot Power Limit Message
Set Slot Power
Limit
(2)
Transmit
Receive No Yes No In Root Port mode, through software.
(2)
Vendor-defined Messages
Vendor Defined Type 0
Transmit
Receive
Transmit
Receive
Yes No No
Vendor Defined Type 1
Transmit
Receive
Transmit
Receive
Yes No No
Table 10–1. Supported Message Types
(2)
(Part 2 of 3)
Message
Root
Port
Endpoint
Generated by
Comments
App
Layer
Core
Core (with
App Layer
input)