User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
10. Transaction Layer Protocol (TLP)
Details
This chapter provides detailed information about the Cyclone V Hard IP for PCI
Express. TLP handling. It includes the following sections:
■ Supported Message Types
■ Transaction Layer Routing Rules
■ Receive Buffer Reordering
Supported Message Types
Table 10–1 describes the message types supported by the Hard IP.
Table 10–1. Supported Message Types
(2)
(Part 1 of 3)
Message
Root
Port
Endpoint
Generated by
Comments
App
Layer
Core
Core (with
App Layer
input)
INTX Mechanism Messages
For Endpoints, only INTA messages are
generated.
Assert_INTA Receive Transmit No Yes No
For Root Port, legacy interrupts are translated
into message interrupt TLPs which triggers
the
int_status[3:0]
signals to the
Application Layer.
■
int_status[0]
: Interrupt signal A
■
int_status[1]
: Interrupt signal B
■
int_status[2]
: Interrupt signal C
■
int_status[3]
: Interrupt signal D
Assert_INTB Receive Transmit No No No
Assert_INTC Receive Transmit No No No
Assert_INTD Receive Transmit No No No
Deassert_INTA Receive Transmit No Yes No
Deassert_INTB Receive Transmit No No No
Deassert_INTC Receive Transmit No No No
Deassert_INTD Receive Transmit No No No
Power Management Messages
PM_Active_State_Nak Transmit Receive No Yes No
PM_PME Receive Transmit No No Yes
PME_Turn_Off Transmit Receive No No Yes
The
pme_to_cr
signal sends and
acknowledges this message:
■ Root Port: When
pme_to_cr
is asserted,
the Root Port sends the PME_turn_off
message.
■ Endpoint: When
pme_to_cr
is asserted,
the Endpoint acknowledges the
PME_turn_off
message by sending a
pme_to_ack
message to the Root Port.
PME_TO_Ack Receive Transmit No No Yes
December 2013
UG-01110-1.5