User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
2–2 Chapter 2: Getting Started with the Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
The Cyclone V Hard IP for PCI Express offers exactly the same feature set in both the
MegaWizard and Qsys design flows. Consequently, your choice of design flow
depends on whether you want to integrate the Cyclone V Hard IP for PCI Express
using RTL instantiation or using Qsys, which is a system integration tool available in
the Quartus II software.
f For more information about Qsys, refer to System Design with Qsys in the Quartus II
Handbook.
h For more information about the Qsys GUI, refer to About Qsys in Quartus II Help.
Figure 2–2 illustrates the steps necessary to customize the Cyclone V Hard IP for PCI
Express and run the example design.
Figure 2–2. MegaWizard Plug-In Manager and Qsys Design Flows
Select Design Flow
Customize the
Hard IP for PCIe
Qsys Flow
MegaWizard Plug-In
Manager Flow
Complete Qsys System
Run Simulation
Create Quartus II Project
Add Quartus IP File (.qip)
Create Quartus II Project
Generate the Simulation
Model for ModelSim, NC-Sim
or VCS
Generate the Simulation
Model in Qsys
Compile the Design for the
Qsys Design Flow
Modify Example Design
to Meet Your Requirements
Compile the Design for the
MegaWizard Design Flow
Add Quartus IP File (.qip)
to Quartus II Project
Customize the
Hard IP for PCIe
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Ye s
No
Simulating?
Ye s
No
Simulating?