User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 8: Register Descriptions 8–21
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
The interrupt status register (Table 8–35) records the status of all conditions that can
cause an Avalon-MM interrupt to be asserted.
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM Interrupt Status
by setting the corresponding bits in the register
(Table 8–36).
PCI Express interrupts can also be enabled for all of the error conditions described.
However, it is likely that only one of the Avalon-MM or PCI Express interrupts can be
enabled for any given bit because typically a single process in either the PCI Express
or Avalon-MM domain that is responsible for handling the condition reported by the
interrupt.
Avalon-MM Mailbox Registers
A processor local to the interconnect fabric typically requires write access to a set of
Avalon-MM-to-PCI Express Mailbox
registers and read-only access to a set of
PCI
Express-to-Avalon-MM Mailbox
registers. Eight mailbox registers are available.
Table 8–35. PCI Express to Avalon-MM Interrupt Status Register for Endpoints 0x3060
Bits Name Access Description
0
ERR_PCI_WRITE_
FAILURE
RW1C
When set to 1, indicates a PCI Express write failure of. This bit can
also be cleared by writing a 1 to the same bit in the
Avalon-MM to
PCI Express Interrupt Status Register
.
1
ERR_PCI_READ_
FAILURE
RW1C
When set to 1, indicates the failure of a PCI Express read. This bit
can also be cleared by writing a 1 to the same bit in the
Avalon-MM
to PCI Express Interrupt Status
register.
[15:2] Reserved — —
[16] P2A_MAILBOX_INT0 RW1C 1 when the P2A_MAILBOX0 is written
[17] P2A_MAILBOX_INT1 RW1C 1 when the P2A_MAILBOX1 is written
[18] P2A_MAILBOX_INT2 RW1C 1 when the P2A_MAILBOX2 is written
[19] P2A_MAILBOX_INT3 RW1C 1 when the P2A_MAILBOX3 is written
[20] P2A_MAILBOX_INT4 RW1C 1 when the P2A_MAILBOX4 is written
[21] P2A_MAILBOX_INT5 RW1C 1 when the P2A_MAILBOX5 is written
[22] P2A_MAILBOX_INT6 RW1C 1 when the P2A_MAILBOX6 is written
[23] P2A_MAILBOX_INT7 RW1C 1 when the P2A_MAILBOX7 is written
[31:24] Reserved — —
Table 8–36. INT-X Interrupt Enable Register for Endpoints 0x3070
Bits Name Access Description
[31:0]
PCI Express to
Avalon-MM Interrupt
Enable
RW
When set to 1, enables the interrupt for the corresponding bit in
the
PCI Express to Avalon-MM Interrupt Status
register
to cause the Avalon Interrupt signal (
craIrq_o
) to be asserted.
Only bits implemented in the PCI
Express to Avalon-MM
Interrupt Status
register are implemented in the Enable
register. Reserved bits cannot be set to a 1.