User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 8: Register Descriptions 8–19
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
The TX TLP programming model scales with the data width. The Application Layer
performs the same writes for both the 64- and 128-bit interfaces. The Application
Layer can only have one outstanding non-posted request at a time. The Application
Layer must use tags 16–31 to identify non-posted requests.
Sending a TLP
The Application Layer performs the following sequence of Avalon-MM accesses to
the CRA slave port to send a Memory Write Request:
1. Write the first 32 bits of the TX TLP to
RP_TX_REG0.
2. Write the next 32 bits of the TX TLP to
RP_TX_REG1.
3. Write the
RP_TX_CNTRL.SOP
to 1’b1 to push the first two dwords of the TLP into the
Root Port TX FIFO.
4. Repeat Steps 1 and 2. The second write to
RP_TX_REG1
is required, even for three
dword TLPs with aligned data.
5. If the packet is complete write
RP_TX_CNTRL
to 2’b10 to indicate the end of the
packet. If the packet is not complete write 2’b00 to
RP_TX_CNTRL.
6. Repeat this sequence to program a complete TLP.
When the programming of the TX TLP is complete, the Avalon-MM Bridge schedules
the TLP with higher priority than TX TLPs coming from the TX slave port.
Receiving a Completion TLP
The Completion TLPs associated with the Non-Posted TX requests are stored in the
RP_RX_CPL FIFO buffer and subsequently loaded into RP_RXCPL registers. The
Application Layer performs the following sequence to retrieve the TLP.
1. Polls the
RP_RXCPL_STATUS.SOP
to determine when it is set to 1’b1.
2. When
RP_RXCPL_STATUS.SOP
= 1’b’1, reads
RP_RXCPL_REG0
and
RP_RXCPL_REG1
to
retrieve dword 0 and dword 1 of the Completion TLP.
3. Read the
RP_RXCPL_STATUS.EOP.
a. If
RP_RXCPL_STATUS.EOP =
1’b0, read
RP_RXCPL_REG0
and
RP_RXCPL_REG1
to
retrieve dword 2 and dword 3 of the Completion TLP, then repeat step 3.
b. If
RP_RXCPL_STATUS.EOP =
1’b1, read
RP_RXCPL_REG0
and
RP_RXCPL_REG1
to
retrieve final dwords of TLP.
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root
Ports
The Root Port supports MSI, MSI-X and legacy (INTx) interrupts. MSI and MSI-X
interrupts are memory writes from the Endpoint to the Root Port. MSI and MSI-X
requests are forwarded to the interconnect without asserting CraIrq_o.