User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 8: Register Descriptions 8–17
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
1 The high performance TLPs implemented by Avalon-MM ports in the Avalon-MM
Bridge are also available for Root Ports. For more information about these TLPs, refer
to Avalon-MM Bridge TLPs. Table 8–32 describes the Root Port TLP data registers.
Programming Model for Avalon-MM Root Port
The Application Layer writes the Root Port TLP TX Data registers with TLP formatted
data for Configuration Read and Write Requests, Message TLPs, I/O Read and Write
Requests, or single dword Memory Read and Write Requests. The Application Layer
data must be in the appropriate TLP format with the data payload aligned to the TLP
address. Aligning the payload data to the TLP address may result in the payload data
being either aligned or unaligned to the qword. Figure 8–1 illustrates three dword
TLPs with data that is aligned and unaligned to the qword.
Table 8–32. Root Port TLP Data Registers 0x2000–0x2FFF
Root-Port Request Registers Address Range: 0x2800-0x2018
Address Bits Name Access Description
0x2000 [31:0]
RP_TX_REG0
RW Lower 32 bits of the TX TLP.
0x2004 [31:0]
RP_TX_REG1
RW Upper 32 bits of the TX TLP.
0x2008
[31:2] Reserved — —
[1]
RX_TX_CNTRL.SOP
RW Write 1’b1 to specify the start of a packet.
[0]
RX_TX_CNTRL.EOP
RW Write 1’b1 to specify the end of a packet.
0x2010
[31:16] Reserved — —
[15:8]
RP_RXCPL_STATUS
RC
Specifies the number of words in the RX
completion FIFO contain valid data.
[7:2] Reserved — —
[1]
RP_RXCPL_STATUS.SOP
RC
When 1’b1, indicates that the data for a
Completion TLP is ready to be read by the
Application Layer. The Application Layer must poll
this bit to determine when a Completion TLP is
available.
[0]
RP_RXCPL_STATUS.EOP
RC
When 1’b1, indicates that the final data for a
Completion TLP is ready to be read by the
Application Layer. The Application Layer must poll
this bit to determine when the final data for a
Completion TLP is available.
0x2014 [31:0]
RP_RXCPL_REG0
R Lower 32 bits of a Completion TLP.
0x2018 [31:0]
RP_RXCPL_REG1
R Upper 32 bits of a Completion TLP.