User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
2. Getting Started with the Cyclone V
Hard IP for PCI Express
This section provides step-by-step instructions to help you quickly customize,
simulate, and compile the Cyclone V Hard IP for PCI Express using either the
MegaWizard Plug-In Manager or Qsys design flow. When you install the Quartus II
software you also install the IP Library. This installation includes design examples for
Hard IP for PCI Express in <install_dir>/ip/altera/altera_pcie/
altera_pcie_hip_ast_ed/example_design/<device> directory.
1 If you have an existing Cyclone V 12.1 or older design, you must regenerate it in 13.1
before compiling with the 13.1 version of the Quartus II software.
After you install the Quartus II software for 13.1, you can copy the design examples
from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/
example_design/<device> directory. This walkthrough uses the Gen1 ×4 Endpoint.
Figure 2–1 illustrates the top-level modules of the testbench in which the DUT, a Gen1
×4 Endpoint, connects to a chaining DMA engine, labeled APPS in Figure 2–1, and a
Root Port model. The Transceiver Reconfiguration Controller dynamically
reconfigures analog settings to optimize signal quality of the serial interface. The
pcie_reconfig_driver drives the Transceiver Reconfiguration Controller. The
simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial
interface.
For a detailed explanation of this example design, refer to Chapter 18, Testbench and
Design Example. If you choose the parameters specified in this chapter, you can run
all of the tests included in Chapter 18.
Figure 2–1. Testbench for an Endpoint
L
APPS
altpcied_sv_hwtcl.v
Stratix V Hard IP for PCI Express Testbench for Endpoints
Avalon-ST TX
Avalon-ST RX
reset
status
Avalon-ST TX
Avalon-ST RX
reset
status
DUT
altpcie_sv_hip_ast_hwtcl.v
Root Port Model
altpcie_tbed_sv_hwtcl.v
PIPE or
Serial
Interface
Root Port BFM
altpcietb_bfm_rpvar_64b_x8_pipen1b
Root Port Driver and Monitor
altpcietb_bfm_vc_intf
December 2013
UG-01110-1.5