User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
8–12 Chapter 8: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Access Content
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Avalon-MM to PCI Express Interrupt Registers
The registers in this section contain status of various signals in the PCI Express
Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when
enabled. Only Root Complexes should access these registers; however, hardware does
not prevent other Avalon-MM masters from accessing them.
Table 8–25 shows the status of all conditions that can cause a PCI Express interrupt to
be asserted.
A PCI Express interrupt can be asserted for any of the conditions registered in the
Avalon-MM to
PCI Express
Interrupt Status
register by setting the corresponding
bits in the Avalon-MM-to-PCI Express
Interrupt Enable
register (Table 8–26). Either
MSI or legacy interrupts can be generated as explained in the section “Enabling MSI
or Legacy Interrupts” on page 11–7.
0x3A00-0x3A1F Avalon-MM-to-PCI Express Mailbox Registers 0x3A00–0x3A1F
0x3B00-0x3B1F PCI Express-to-Avalon-MM Mailbox Registers 0x3B00–0x3B1F
Table 8–24. PCI Express Avalon-MM Bridge Register Map (Part 2 of 2)
Address Range Register
Table 8–25. Avalon-MM to PCI Express Interrupt Status Register 0x0040
Bit Name Access Description
31:24 Reserved — —
23
A2P_MAILBOX_INT7
RW1C 1 when the A2P_MAILBOX7 is written to
22
A2P_MAILBOX_INT6
RW1C 1 when the A2P_MAILBOX6 is written to
21
A2P_MAILBOX_INT5
RW1C 1 when the A2P_MAILBOX5 is written to
20
A2P_MAILBOX_INT4
RW1C 1 when the A2P_MAILBOX4 is written to
19
A2P_MAILBOX_INT3
RW1C 1 when the A2P_MAILBOX3 is written to
18
A2P_MAILBOX_INT2
RW1C 1 when the A2P_MAILBOX2 is written to
17
A2P_MAILBOX_INT1
RW1C 1 when the A2P_MAILBOX1 is written to
16
A2P_MAILBOX_INT0
RW1C 1 when the A2P_MAILBOX0 is written to
[15:0] AVL_IRQ_ASSERTED[15:0] RO
Current value of the Avalon-MM interrupt (IRQ) input
ports to the Avalon-MM RX master port:
■ 0 – Avalon-MM IRQ is not being signaled.
■ 1 – Avalon-MM IRQ is being signaled.
A Qsys-generated IP Compiler for PCI Express has as
many as 16 distinct IRQ input ports. Each
AVL_IRQ_ASSERTED[] bit reflects the value on the
corresponding IRQ input port.