User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 8: Register Descriptions 8–9
Altera-Defined Vendor Specific Extended Capability (VSEC)
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Table 8–19 defines the fields of the
Uncorrectable Internal Error Status
register.
This register reports the status of the internally checked errors that are uncorrectable.
When specific errors are enabled by the
Uncorrectable Internal Error Mask
register, they are handled as Uncorrectable Internal Errors as defined in the PCI
Express Base Specification 3.0. This register is for debug only. It should only be used to
observe behavior, not to drive logic custom logic.
Table 8–20 defines the
Uncorrectable Internal Error Mask
register. This register
controls which errors are forwarded as internal uncorrectable errors. With the
exception of the configuration error detected in CvP mode, all of the errors are severe
and may place the device or PCIe link in an inconsistent state. The configuration error
detected in CvP mode may be correctable depending on the design of the
programming software.
Table 8–19. Uncorrectable Internal Error Status Register
Bits Register Description Access
[31:12] Reserved. RO
[11] When set, indicates an RX buffer overflow condition in a posted request or Completion RW1CS
[10] Reserved. RO
[9] When set, indicates a parity error was detected on the Configuration Space to TX bus interface RW1CS
[8] When set, indicates a parity error was detected on the TX to Configuration Space bus interface RW1CS
[7] When set, indicates a parity error was detected in a TX TLP and the TLP is not sent. RW1CS
[6] When set, indicates that the Application Layer has detected an uncorrectable internal error. RW1CS
[5]
When set, indicates a configuration error has been detected in CvP mode which is reported as
uncorrectable. This bit is set whenever a
CVP_CONFIG_ERROR
rises while in
CVP_MODE
.
RW1CS
[4] When set, indicates a parity error was detected by the TX Data Link Layer. RW1CS
[3]
When set, indicates a parity error has been detected on the RX to Configuration Space bus
interface.
RW1CS
[2] When set, indicates a parity error was detected at input to the RX Buffer. RW1CS
[1] When set, indicates a retry buffer uncorrectable ECC error. RW1CS
[0] When set, indicates a RX buffer uncorrectable ECC error. RW1CS
Table 8–20. Uncorrectable Internal Error Mask Register (Part 1 of 2)
Bits Register Description Reset Value Access
[31:12] Reserved. 1b’0 RO
[11] Mask for RX buffer posted and completion overflow error. 1b’1 RWS
[10] Reserved 1b’0 RO
[9] Mask for parity error detected on Configuration Space to TX bus interface. 1b’1 RWS
[8] Mask for parity error detected on the TX to Configuration Space bus interface. 1b’1 RWS
[7] Mask for parity error detected at TX Transaction Layer error. 1b’1 RWS
[6] Reserved 1b’0 RO
[5] Mask for configuration errors detected in CvP mode. 1b’0 RWS
[4] Mask for data parity errors detected during TX Data Link LCRC generation. 1b’1 RWS
[3]
Mask for data parity errors detected on the RX to Configuration Space Bus
interface.
1b’1 RWS