User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
8–8 Chapter 8: Register Descriptions
Altera-Defined Vendor Specific Extended Capability (VSEC)
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 8–17 defines the
CvP Data
register. Programming software should write the
configuration data to this register. Every write to this register sets the data output to
the FPGA control block and generates <n> clock cycles to the FPGA control block as
specified by the
CVP_NUM_CLKS
field in the
CvP Mode
Control
register. Software must
ensure that all bytes in the memory write dword are enabled. You can access this
register using configuration writes, alternatively, when in CvP mode, this register can
also be written by a memory write to any address defined by a memory space BAR for
this device. Using memory writes should allow for higher throughput than
configuration writes.
Table 8–18 defines the
CvP Programming Control
register. This register is written by
the programming software to control CvP programming.
f Refer to Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide for
more information about using CvP.
[1]
HIP_CLK_SEL
. Selects between PMA and fabric clock when
USER_MODE
= 1 and
PLD_CORE_READY
= 1. The following encodings are defined:
■ 1: Selects internal clock from PMA which is required for CVP_MODE
■ 0: Selects the clock from soft logic fabric. This setting should only be used
when the fabric is configured in
USER_MODE
with a configuration file that
connects the correct clock.
To ensure that there is no clock switching during CvP, you should only change
this value when the Hard IP for PCI Express has been idle for 10
s and wait
10
s after changing this value before resuming activity.
1’b0 RW
[0]
CVP_MODE
. Controls whether the HIP is in CVP_MODE or normal mode. The
following encodings are defined:
■ 1: CVP_MODE is active. Signals to the FPGA control block active and all TLPs
are routed to the Configuration Space. This
CVP_MODE
cannot be enabled if
CVP_EN
= 0.
■ 0: The IP core is in normal mode and TLPs are route to the FPGA fabric.
1’b0 RW
Table 8–16. CvP Mode Control (Part 2 of 2)
Bits Register Description Reset Value Access
Table 8–17. CvP Data Register
Bits Register Description Reset Value Access
[31:0]
Configuration data to be transferred to the FPGA control block to configure the
device.
0x00000000 RW
Table 8–18. CvP Programming Control Register
Bits Register Description Reset Value Access
[31:2] Reserved. 0x0000 RO
[1]
START_XFER
. Sets the CvP output to the FPGA control block indicating the start
of a transfer.
1’b0 RW
[0]
CVP_CONFIG
. When asserted, instructs that the FPGA control block begin a
transfer via CvP.
1’b0 RW