User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 8: Register Descriptions 8–7
Altera-Defined Vendor Specific Extended Capability (VSEC)
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Table 8–15 defines the fields of the
CvP Status
register. This register allows software
to monitor the CvP status signals.
Table 8–16 defines the fields of the CvP Mode Control register which provides global
control of the CvP operation.
f Refer to Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide for
more information about using CvP.
Table 8–15. CvP Status
Bits Register Description Reset Value Access
[15:10] Reserved. 0x00 RO
[9]
PLD_CORE_READY
. From FPGA fabric. This status bit is provided for debug. Variable RO
[8]
PLD_CLK_IN_USE
. From clock switch module to fabric. This status bit is
provided for debug.
Variable RO
[7]
CVP_CONFIG_DONE
. Indicates that the FPGA control block has completed the
device configuration via CvP and there were no errors.
Variable RO
[6]
CVP_HF_RATE_SEL
. Indicates if the FPGA control block interface to the
Cyclone V Hard IP for PCI Express is operating half the normal
frequency–62.5MHz, instead of full rate of 125MHz
Variable RO
[5]
USERMODE
. Indicates if the configurable FPGA fabric is in user mode. Variable RO
[4]
CVP_EN
. Indicates if the FPGA control block has enabled CvP mode. Variable RO
[3]
CVP_CONFIG_ERROR
. Reflects the value of this signal from the FPGA control
block, checked by software to determine if there was an error during
configuration
Variable RO
[2]
CVP_CONFIG_READY – reflects the value of this signal from the FPGA control
block, checked by software during programming algorithm
Variable RO
[1] Reserved. — —
[0] Reserved. — —
Table 8–16. CvP Mode Control (Part 1 of 2)
Bits Register Description Reset Value Access
[31:16] Reserved. 0x0000 RO
[15:8]
CVP_NUMCLKS
. Specifies the number of CvP clock cycles required for every CvP
data register write. Valid values are 0x00–0x3F, where 0x00 corresponds to 64
cycles, and 0x01-0x3F corresponds to 1 to 63 clock cycles. The upper bits are
not used, but are included in this field because they belong to the same byte
enable.
0x00 RW
[7:4] Reserved. 0x0 RO
[2]
CVP_FULLCONFIG
. Request that the FPGA control block reconfigure the entire
FPGA including the Cyclone V Hard IP for PCI Express, bring the PCIe link down.
1’b0 RW