User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
8–4 Chapter 8: Register Descriptions
Configuration Space Register Content
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 8–6 describes the Power Management Capability structure.
Table 8–7 describes the PCI Express AER Extended Capability structure.
Table 8–8 describes the PCI Express Capability Structure.
Table 8–6. Power Management Capability Structure, Rev2.1 Spec
Byte Offset 31:24 23:16 15:8 7:0
0x078 Capabilities Register Next Cap PTR Cap ID
0x07C Data
PM Control/Status
Bridge Extensions
Power Management Status & Control
Note to Table 8–6:
(1) Refer to Table 8–39 on page 8–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.1.
Table 8–7. PCI Express AER Capability Structure, Rev2.1 Spec: Advanced Error Reporting Capability
Byte Offset 31:24 23:16 15:8 7:0
0x800 PCI Express Enhanced Capability Header
0x804 Uncorrectable Error Status Register
0x808 Uncorrectable Error Mask Register
0x80C Uncorrectable Error Severity Register
0x810 Correctable Error Status Register
0x814 Correctable Error Mask Register
0x818 Advanced Error Capabilities and Control Register
0x81C Header Log Register
0x82C Root Error Command
0x830 Root Error Status
0x834 Error Source Identification Register Correctable Error Source ID Register
Note to Table 8–7:
(1) Refer to Table 8–39 on page 8–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.1.
Table 8–8. PCIe Capability Structure 2.1, Rev2.1 Spec (Part 1 of 2)
Byte Offset 31:16 15:8 7:0
0x080 PCI Express Capabilities Register Next Cap Pointer PCI Express Cap ID
0x084 Device Capabilities
0x088 Device Status Device Control
0x08C Link
0x090 Link Status Link Control
0x094 Slot
0x098 Slot Status Slot Control
0x09C Root Capabilities Root Control
0x0A0 Root Status
0x0A4 Device Capabilities 2