User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
7–42 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 7–17 shows the layout of the Power Management Capabilities register.
Table 7–18 describes the use of the various fields of the Power Management
Capabilities register.
Figure 7–34 illustrates the behavior of
pme_to_sr
and
pme_to_cr
in an Endpoint. First,
the Hard IP receives the
PME_turn_off
message which causes
pme_to_sr
to assert.
Then, the Application Layer sends the
PME_to_ack
message to the Root Port by
asserting
pme_to_cr
.
Table 7–17. Power Management Capabilities Register
31 24 22 16 15 14 13 12 9 8 7 2 1 0
data
register
rsvd PME_status data_scale data_select PME_EN rsvd PM_state
Table 7–18. Power Management Capabilities Register Field Descriptions
Bits Field Description
[31:24]
Data register
This field indicates in which power states a function can assert the
PME# message
.
[22:16]
reserved
—
[15]
PME_status
When set to 1, indicates that the function would normally assert the
PME#
message
independently of the state of the
PME_en
bit.
[14:13]
data_scale
This field indicates the scaling factor when interpreting the value retrieved from the data
register. This field is read-only.
[12:9]
data_select
This field indicates which data should be reported through the data register and the
data_scale
field.
[8]6
PME_EN
1: indicates that the function can assert PME#
0: indicates that the function cannot assert PME#
[7:2]
reserved
—
[1:0]
PM_state
Specifies the power management state of the operating condition being described. The
following encodings are defined:
■ 2b’00 D0
■ 2b’01 D1
■ 2b’10 D2
■ 2b’11 D3
A device returns 2b’11 in this field and
Aux
or
PME Aux
in the
type
register to specify
the D3-Cold PM state. An encoding of 2b’11 along with any other
type
register value
specifies the D3-Hot state.
Figure 7–34. pme_to_sr and pme_to_cr in an Endpoint IP core
pme_to_sr
pme_to_cr
hard
IP