User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
7–32 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
tl_cfg_sts[122:0]
0
Configuration status bits. This information updates every
pld_clk
cycle. Bits[52:0] record
status information for function0. Bits[62:53] record information for function1. Bits[72:63]
record information for function 2, and so on. Refer to Table 7–11 for a detailed description
of the status bits.
tl_cfg_sts_wr
0
Write signal. This signal toggles when
tl_cfg_sts
has been updated (every 8
core_clk
cycles). The toggle marks the edge where
tl_cfg_sts
data changes. You can use this
edge as a reference to determine when the data is safe to sample.
tl_hpg_ctrl_er[4:0]
I
The tl_
hpg_ctrl_er
signals are only available in Root Port mode and when the Slot
Capability register is enabled. Refer to the Use Slot register parameter in Table 4–5 on
page 4–6. For Endpoint variations the
tl_hpg_ctrl_er
input should be hardwired to 0s.
The bits have the following meanings:
■ [0]: Attention button pressed. This signal should be asserted when the attention button
is pressed. If no attention button exists for the slot, this bit should be hardwired to 0,
and the
Attention Button Present
bit (bit[0]) in the Slot Capability register is set
to 0.
■ [1]: Presence detect. This signal should be asserted when a presence detect circuit
detects a presence change in the slot.
■ [2]: Manually-operated retention latch (MRL) sensor changed. This signal should be
asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does
not exist for the slot, this bit should be hardwired to 0, and the
MRL
Sensor
Present
bit
(bit[2]) in the Slot Capability register is to 0.
■ [3]:Power fault detected. This signal should be asserted when the power controller
detects a power fault for this slot. If this slot has no power controller, this bit should be
hardwired to 0, and the
Power
Controller
Present
bit (bit[1]) in the Slot Capability
register is set to 0.
■ [4]: Power controller status. This signal is used to set the command completed bit of
the
Slot
Status
register. Power controller status is equal to the power controller
control signal. If this slot has no power controller, this bit should be hardwired to 0 and
the
Power Controller Present
bit (bit[1]) in the Slot Capability register is set to 0.
Table 7–10. Configuration Space Signals (Hard IP Implementation) (Part 2 of 2)
Signal Dir Description