User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
7–30 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 7–9. Completion Signals for the Avalon-ST Interface (Part 1 of 2)
Signal I/O Description
cpl_err[6:0]
I
Completion error. This signal reports completion errors to the Configuration
Space. When an error occurs, the appropriate signal is asserted for one cycle.
■
cpl_err[0]
: Completion timeout error with recovery. This signal should be
asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
timeout period when the error is correctable. The Hard IP automatically
generates an advisory error message that is sent to the Root Complex.
■
cpl_err[1]
: Completion timeout error without recovery. This signal should
be asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
time-out period when the error is not correctable. The Hard IP automatically
generates a non-advisory error message that is sent to the Root Complex.
■ Completer abort error. The Application Layer asserts this signal to respond to
a non-posted request with a Completer Abort (CA) completion. The
Application Layer generates and sends a completion packet with Completer
Abort (CA) status to the requestor and then asserts this error signal to the
Hard IP. The Hard IP automatically sets the error status bits in the
Configuration Space register and sends error messages in accordance with
the
PCI Express Base Specification, Rev. 2.1.
■
cpl_err[3]
: Unexpected completion error. This signal must be asserted
when an Application Layer master block detects an unexpected completion
transaction. Many cases of unexpected completions are detected and reported
internally by the Transaction Layer. For a list of these cases, refer to
“Transaction Layer Errors” on page 14–3.
■
cpl_err[4]
: Unsupported Request (UR) error for posted TLP. The
Application Layer asserts this signal to treat a posted request as an
Unsupported Request. The Hard IP automatically sets the error status bits in
the Configuration Space register and sends error messages in accordance
with the
PCI Express Base Specification. Many cases of Unsupported
Requests are detected and reported internally by the Transaction Layer. For a
list of these cases, refer to “Transaction Layer Errors” on page 14–3.
■
cpl_err[5]
: Unsupported Request error for non-posted TLP. The Application
Layer asserts this signal to respond to a non-posted request with an
Unsupported Request (UR) completion. In this case, the Application Layer
sends a completion packet with the Unsupported Request status back to the
requestor, and asserts this error signal. The Hard IP automatically sets the
error status bits in the Configuration Space Register and sends error
messages in accordance with the
PCI Express Base Specification. Many
cases of Unsupported Requests are detected and reported internally by the
Transaction Layer. For a list of these cases, refer to “Transaction Layer Errors”
on page 14–3.