User guide

7–26 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
pld_clk_inuse O
When asserted, indicates that the Hard IP Transaction Layer is using the
pld_clk as its
clock and is ready for operation with the Application Layer. For reliable operation, hold the
Application Layer in reset until
pld_clk_inuse is asserted.
Do not drive data input to the Hard IP before
pld_clk_inuse is asserted. pld_clk_inuse
and
pld_core_ready are typically used as handshaking signals after programming the
FPGA fabric with CvP. These handshaking signals ensure a reliable Hard IP clock switchover
from an internal clock used during the CvP operation to the
pld_clk Hard IP input clock.
dlup_exit O
This signal is active for one
pld_clk cycle when the IP core exits the DLCMSM DL_Up state,
indicating that the Data Link Layer has lost communication with the other end of the PCIe
link and left the Up state. This signal should cause the Application Layer to assert a global
reset. This signal is active low and otherwise remains high.
ev128ns O Asserted every 128 ns to create a time base aligned activity.
ev1us O Asserted every 1 µs to create a time base aligned activity.
hotrst_exit O
Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset
state. This signal should cause the Application Layer to assert a global reset to its logic. This
signal is active low and otherwise remains high.
l2_exit O
L2 exit. This signal is active low and otherwise remains high. It is asserted for one cycle
(changing value from 1 to 0 and back to 1) after the LTSSM transitions from l2_idl to detect.
current_speed O
Indicates the current speed of the PCIe link. The following encodings are defined:
■ 2b’00: Reserved
■ 2b’01: Gen1
■ 2’b10: Gen2
■ 2’b11: Gen3
Table 7–6. Reset and Link Training Signals (Part 2 of 3)
Signal I/O Description