User guide

7–24 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
To ensure proper operation when sending Configuration Type 0 transactions in Root
Port mode, the application should wait for the Configuration Type 0 transaction to be
transferred to the Hard IP for PCI Express Configuration Space before issuing another
packet on the Avalon-ST TX port. You can do this by waiting for the core to respond
with a completion on the Avalon-ST RX port before issuing the next Configuration
Type 0 transaction.
ECRC Forwarding
On the Avalon-ST interface, the ECRC field follows the same alignment rules as
payload data. For packets with payload, the ECRC is appended to the data as an extra
dword of payload. For packets without payload, the ECRC field follows the address
alignment as if it were a one dword payload. Depending on the address alignment,
Figure 7–7 on page 7–10 through Figure 7–14 on page 7–14 illustrate the position of
the ECRC data for RX data. Figure 7–18 on page 7–19 through Figure 7–26 on
page 7–22 illustrate the position of ECRC data for TX data. For packets with no
payload data, the ECRC corresponds to the position of Data0 in these figures.
Clock Signals
Table 7–5 describes the clock signals that comprise the clock interface.
Refer to Chapter 9, Reset and Clocks for more information about the clock interface.
Table 7–5. Clock Signals Hard IP Implementation
(1)
Signal I/O Description
refclk I
Reference clock for the Cyclone V Hard IP for PCI Express. It must have the frequency
specified under the System Settings heading in the parameter editor.
If your design meets the following criteria:
■ It enables CvP
■ Includes an additional transceiver PHY connected to the same Transceiver Reconfiguration
Controller
then you must connect
refclk to the mgmt_clk_clk signal of the Transceiver
Reconfiguration Controller and the additional transceiver PHY. In addition, if your design
includes more than one Transceiver Reconfiguration Controller on the same side of the FPGA,
they all must share the
mgmt_clk_clk signal.
pld_clk I Clocks the Application Layer. You must drive this clock with coreclkout_hip .
coreclkout_hip O
This is a fixed frequency clock used by the Data Link and Transaction Layers. To meet PCI
Express link bandwidth constraints, this clock has minimum frequency requirements as listed
in Table 9–2 on page 9–6.
Note to Table 7–5:
(1) Figure 9–5 on page 9–5 illustrates these clock signals.