User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 7: IP Core Interfaces 7–23
Cyclone V Hard IP for PCI Express
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Figure 7–27 illustrates back-to-back transmission of 128-bit packets with no idle cycles
between the assertion of
tx_st_eop
and
tx_st_sop
.
Figure 7–28 illustrates the timing of the TX interface when the Cyclone V Hard IP for
PCI Express IP core backpressures the Application Layer by deasserting
tx_st_ready
.
Because the
readyLatency
is two cycles, the Application Layer deasserts
tx_st_valid
after two cycles.
Root Port Mode Configuration Requests
If your Application Layer implements ECRC forwarding, it should not apply ECRC
forwarding to Configuration Type 0 packets that it issues on the Avalon-ST interface.
There should be no ECRC appended to the TLP, and the
TD
bit in the TLP header
should be set to 0. These packets are processed internally by the Hard IP block and
are not transmitted on the PCI Express link.
Figure 7–27. 128-Bit Back-to-Back Transmission on the Avalon-ST TX Interface
coreclkout
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7–28. 128-Bit Hard IP Backpressures the Application Layer
coreclkout
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
000 CC... CC... CC... . CC... CC... CC... CC... CC... CC... CC... CC...