User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
7–18 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
tx_cred_fchipcons
6O
component
specific
Asserted for 1 cycle each time the Hard IP consumes a
credit. The 6 bits of this vector correspond to the following
6 types of credit types:
■ [5]: posted headers
■ [4]: posted data
■ [3]: non-posted header
■ [2]: non-posted data
■ [1]: completion header
■ [0]: completion data
During a single cycle, the Hard IP can consume either a
single header credit or both a header and a data credit. The
Application Layer must keep track of credits consumed by
the Application Layer logic.
tx_cred_fc_infinite
6O
component
specific
When asserted, indicates that the corresponding credit
type has infinite credits available and does not need to
calculate credit limits. The 6 bits of this vector correspond
to the following 6 types of credit types:
■ [5]: posted headers
■ [4]: posted data
■ [3]: non-posted header
■ [2]: non-posted data
■ [1]: completion header
■ [0]: completion data
tx_cred_hdrfccp
8O
component
specific
Header credit limit for transmission of completions. Each
credit is 20 bytes.
tx_cred_hdrfcnp
8O
component
specific
Header limit for transmission of non-posted requests. Each
credit is 20 bytes.
tx_cred_hdrfcp
8O
component
specific
Header credit limit for transmission of posted writes. Each
credit is 20 bytes.
ko_cpl_spc_header
8O
component
specific
ko_cpl_spc_header
is a static signal that indicates the
total number of completion headers that can be stored in
the RX buffer. The Application Layer can use this signal to
build circuitry to prevent RX buffer overflow for completion
headers. Endpoints must advertise infinite space for
completion headers; however, RX buffer space is finite.
Table 7–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 3 of 4)
Signal Width Dir
Avalon-ST
Type
Description