User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 7: IP Core Interfaces 7–17
Cyclone V Hard IP for PCI Express
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
tx_st_valid
(1)
1I
valid
Clocks
tx_st_data
to the Hard IP when
tx_st_ready
is
also asserted. Between
tx_st_sop
and
tx_st_eop
,
tx_st_valid
can be asserted only if
tx_st_ready
is
asserted. When
tx_st_ready
deasserts, this signal must
deassert within 1 or 2 clock cycles. When
tx_st_ready
reasserts, and
tx_st_data
is in mid-TLP, this signal must
reassert within 2 cycles. Refer to Figure 7–21 on
page 7–20 for the timing of this signal.
To facilitate timing closure, Altera recommends that you
register both the
tx_st_ready
and
tx_st_valid
signals.
If no other delays are added to the ready-valid latency, the
resulting delay corresponds to a
readyLatency
of 2.
tx_st_empty
1I
empty
Indicates the number of qwords that are empty during
cycles that contain the end of a packet. When asserted, the
empty qwords are in the high-order bits. Valid only when
tx_st_eop
is asserted.
Not used when
tx_st_data
is 64 bits. When asserted,
indicates that the upper qword is empty, does not contain
valid data.
tx_st_err
1I
error
Indicates an error on transmitted TLP. This signal is used to
nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert
this signal for 1 cycle after the SOP and before the EOP.
When a packet is nullified, the following packet should not
be transmitted until the next clock cycle.
tx_st_err
is not
available for packets that are 1 or 2 cycles long. The error
signal must be asserted while the valid signal is asserted.
Component Specific Signals
tx_fifo_empty
1O
component
specific
When asserted high, indicates that the TX FIFO is empty.
tx_cred_datafccp
12 O
component
specific
Data credit limit for transmission of completions. Each
credit is 16 bytes.
tx_cred_datafcnp
12 O
component
specific
Data credit limit for transmission of non-posted requests.
Each credit is 16 bytes.
tx_cred_datafcp
12 O
component
specific
Data credit limit for transmission of posted writes. Each
credit is 16 bytes.
Table 7–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 2 of 4)
Signal Width Dir
Avalon-ST
Type
Description