User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 1: Datasheet 1–3
Features
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
f The purpose of the Cyclone V Hard IP for PCI Express User Guide is to explain how to
use the Cyclone V Hard IP for PCI Express and not to explain the PCI Express
protocol. Although there is inevitable overlap between these two purposes, this
document should be used in conjunction with an understanding of the following PCI
Express specifications: PHY Interface for the PCI Express Architecture PCI Express 2.0 and
PCI Express Base Specification 2.1.
Transaction Layer Packet Types (TLP) (3)
■ Memory Read Request
■ Memory Read Request-Locked
■ Memory Write Request
■ I/O Read Request
■ I/O Write Request
■ Configuration Read Request
(Root Port)
■ Configuration Write Request
(Root Port)
■ Message Request
■ Message Request with Data
Payload
■ Completion without Data
■ Completion with data
■ Completion for Locked Read
without Data
■ Memory Read Request
■ Memory Write Request
■ Configuration Read Request
(Root Port)
■ Configuration Write Request
(Root Port)
■ Message Request
■ Message Request with Data
Payload
■ Completion without Data
■ Completion with Data
■ Memory Read Request (single
dword)
■ Memory Write Request (single
dword)
Maximum payload size 128–512 bytes 128–256 bytes
Number of tags supported for non-posted
requests
32 or 64 8
62.5 MHz clock Supported Supported
Multi-function
Supports up to 8 functions Supports single function only
Polarity inversion of PIPE interface signals Supported Supported
ECRC forwarding on RX and TX Supported Not supported
Expansion ROM Supported Not supported
Number of MSI requests 16 1, 2, 4, 8, or 16
MSI-X Supported Supported
Multiple MSI, MSI-X, and INTx Not Supported Supported
Legacy interrupts Supported Supported
Notes to Table 1–2:
(1) Not recommended for new designs.
(2) ×2 is supported by down training from ×4 or ×8 lanes.
(3) Refer to Appendix A, Transaction Layer Packet (TLP) Header Formats for the layout of TLP headers.
Table 1–1. Differences in Features Available Using the Avalon-MM and Avalon-ST Interfaces (Part 2 of 2)
Feature Avalon-ST Interface Avalon-MM Interface