User guide
Table Of Contents
- Cyclone V Hard IP for PCI Express User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Cyclone V Hard IP for PCI Express
- 3. Getting Started with the Avalon-MM Cyclone Hard IP for PCI Express
- Running Qsys
- Customizing the Cyclone VHard IP for PCI Express IP Core
- Adding the Remaining Components to the Qsys System
- Completing the Connections in Qsys
- Specifying Clocks and Interrupts
- Specifying Exported Interfaces
- Specifying Address Assignments
- Simulating the Example Design
- Simulating the Single DWord Design
- Understanding Channel Placement Guidelines
- Adding Synopsis Design Constraints
- Creating a Quartus II Project
- Compiling the Design
- Programming a Device
- 4. Parameter Settings for the Cyclone V Hard IP for PCI Express
- 5. Parameter Settings for the Avalon-MM Cyclone V Hard IP for PCI Express
- 6. IP Core Architecture
- Key Interfaces
- Protocol Layers
- Multi-Function Support
- PCI Express Avalon-MM Bridge
- Avalon-MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for Endpoints
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm
- Single DWord Completer Endpoint
- 7. IP Core Interfaces
- Cyclone V Hard IP for PCI Express
- Avalon-MM Hard IP for PCI Express
- Physical Layer Interface Signals
- Test Signals
- 8. Register Descriptions
- Configuration Space Register Content
- Altera-Defined Vendor Specific Extended Capability (VSEC)
- PCI Express Avalon-MM Bridge Control Register Access Content
- Avalon-MM to PCI Express Interrupt Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- Root Port TLP Data Registers
- Programming Model for Avalon-MM Root Port
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Correspondence between Configuration Space Registers and the PCIe Spec 2.1
- 9. Reset and Clocks
- 10. Transaction Layer Protocol (TLP) Details
- 11. Interrupts
- Interrupts for Endpoints Using the Avalon-ST Application Interface
- Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
- Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
- Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
- 12. Optional Features
- 13. Flow Control
- 14. Error Handling
- 15. Transceiver PHY IP Reconfiguration
- 16. SDC Timing Constraints
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- Additional Information
Chapter 7: IP Core Interfaces 7–11
Cyclone V Hard IP for PCI Express
December 2013 Altera Corporation Cyclone V Hard IP for PCI Express
User Guide
Figure 7–8 shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs
for a four dword header with non-qword addresses with a 64-bit bus. Note that the
address of the first dword is 0x4. The address of the first enabled byte is 0x6. This
example shows one valid word in the first dword, as indicated by the
rx_st_be
signal.
Figure 7–9 illustrates the timing of the RX interface when the Application Layer
backpressures the Cyclone V Hard IP for PCI Express by deasserting
rx_st_ready
.
The
rx_st_valid
signal must deassert within three cycles after
rx_st_ready
is
deasserted. In this example,
rx_st_valid
is deasserted in the next cycle.
rx_st_data
is
held until the Application Layer is able to accept it.
Figure 7–8. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLP with Non-Qword Address
(1)
Note to Figure 7–8:
(1)
rx_st_be[7:4]
corresponds to
rx_st_data[63:32]
.
rx_st_be[3:0]
corresponds to
rx_st_data[31:0]
.
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bar[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
header1 header3 data0 data2
header0 header2 data1
10
C F
F
Figure 7–9. 64-Bit Application Layer Backpressures Transaction Layer for RX Transactions
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bardec[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
header0 header2 data1
10
C F
F