User guide

7–6 Chapter 7: IP Core Interfaces
Cyclone V Hard IP for PCI Express
Cyclone V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
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1 The PCI Express Base Specification 2.1 states that receivers may optionally check the
address translation (AT) bits in byte 2 of the header and flag the received TLP as
malformed if AT is not equal to is 2b’00. The Cyclone V Hard IP for PCI Express IP
core does not perform this optional check.
Avalon-ST RX Interface
Table 7–3 describes the signals that comprise the Avalon-ST RX Datapath. The RX data
signal can be 64 or 128 bits.
Figure 7–4. Qword Alignment
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0x0
0x8
0x10
0x18
Header Addr = 0x4
64 bits
PCB Memory
Valid Data
Valid Data
Table 7–3. 64- or 128-Bit Avalon-ST RX Datapath (Part 1 of 4)
Signal Width Dir
Avalon-ST
Type
Description
rx_st_data
6412
8
O
data
Receive data bus. Refer to the figures below for the mapping of
the Transaction Layer’s TLP information to
rx_st_data and
examples of the timing of this interface. Note that the position
of the first payload dword depends on whether the TLP address
is qword aligned. The mapping of message TLPs is the same as
the mapping of TLPs with 4 dword headers. When using a 64-
bit Avalon-ST bus, the width of
rx_st_data is 64. When using
a 128-bit Avalon-ST bus, the width of
rx_st_data is 128.
rx_st_sop 1O
start of
packet
Indicates that this is the first cycle of the TLP when
rx_st_valid is asserted.
rx_st_eop 1O
end of
packet
Indicates that this is the last cycle of the TLP when
rx_st_valid is asserted.
rx_st_empty 1O empty
Indicates the number of empty qwords in rx_st_data . Not
used when
rx_st_data is 64 bits.
When asserted, indicates that the upper qword is empty, does
not contain valid data.
rx_st_ready 1I ready
Indicates that the Application Layer is ready to accept data. The
Application Layer deasserts this signal to throttle the data
stream.
If
rx_st_ready is asserted by the Application Layer on cycle
<n>, then <n +
readyLatency > is a ready cycle, during which
the Transaction Layer may assert
valid and transfer data.
The RX interface supports a
readyLatency of 2 cycles.