User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 99
UG197 (v1.5) July 22, 2009
Integrated Endpoint Block Attributes
R
L0SEXITLATENCYCOMCLK
Integer Sets the exit latency from the L0s state to be applied
where a common clock is used. Transferred to the
Link Capabilities register. Possible values are:
0: less than 64 ns
1: 64 ns to less than 128 ns
2: 128 ns to less than 256 ns
3: 256 ns to less than 512 ns
4: 512 ns to less than 1 µs
5: 1 µs to less than 2 µs
6: 2 µs to 4 µs
7: more than 4 µs
L1EXITLATENCY
Integer Sets the exit latency from the L1 state to be applied
where separate clocks are used. Transferred to the
Link Capabilities register. Possible values are:
0: less than 1 µs
1: 1 µs to less than 2 µs
2: 2 µs to less than 4 µs
3: 4 µs to less than 8 µs
4: 8 µs to less than 16 µs
5: 16 µs to less than 32 µs
6: 32 µs to 64 µs
7: more than 64 µs
L1EXITLATENCYCOMCLK
Integer Sets the exit latency from the L1 state to be applied
where a common clock is used. Transferred to the
Link Capabilities register. Possible values are:
0: less than 1 µs
1: 1 µs to less than 2 µs
2: 2 µs to less than 4 µs
3: 4 µs to less than 8 µs
4: 8 µs to less than 16 µs
5: 16 µs to less than 32 µs
6: 32 µs to 64 µs
7: more than 64 µs
BAR0EXIST
Boolean TRUE specifies that Base Address Register 0 exists.
BAR1EXIST
Boolean TRUE specifies that Base Address Register 1 exists.
BAR2EXIST
Boolean TRUE specifies that Base Address Register 2 exists.
BAR3EXIST
Boolean TRUE specifies that Base Address Register 3 exists.
BAR4EXIST
Boolean TRUE specifies that Base Address Register 4 exists.
BAR5EXIST
Boolean TRUE specifies that Base Address Register 5 exists.
BAR0ADDRWIDTH
Integer Specifies BAR 0 address width. Valid settings are:
0: 32 bits wide
1: 64 bits wide
When 64-bit addressing is selected, the BAR
occupies both the BAR0 and the BAR1 registers.
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description