User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 93
UG197 (v1.5) July 22, 2009
Initial Flow Control Credits
R
The write latency attribute settings are calculated as:
# of fabric write pipeline stages (address and data)
+1
Write Latency Setting
The allowed settings are given Table A-3.
Initial Flow Control Credits
Initial flow control credits attributes should be set according to Table A-4.
Note:
• Endpoints are required to advertise infinite completions. The integrated Endpoint
block can use completion flow control, but this choice should only be made if the user
knows that the link partner can receive completion flow control updates from an
Endpoint. See the section entitled “Performance Considerations on Receive
Transaction Interface” in UG341
, LogiCORE IP Endpoint Block Plus for PCI Express User
Guide.
Table A-2: Memory Interface Read Latency Settings
Block RAM
Output
Registers Used
Number of
Fabric Pipeline
Stages (Data)
Number of Fabric
Pipeline Stages
(Address/Control)
TLRAMREADLATENCY or
RETRYRAMREADLATENCY
Setting
Notes
10 0 011b Typical setting
11 1 101b
For very large buffer sizes
implemented in slow speed
grade parts
Tab le A -3 : Memory Interface Write Latency Settings
Number of Fabric
Pipeline Stages
(Address and Data)
TLRAMWRITELATENCY or
RETRYRAMWRITELATENCY
Setting
Notes
0 001b Typical setting.
1 010b
For very large buffer sizes implemented
in slower speed grade devices.
Table A-4: Flow Control Attribute Settings
Attribute Value
VC0TOTALCREDITSPH Maximum of 8
VC0TOTALCREDITSNPH Maximum of 8
VC0TOTALCREDITSCH 0 if
INFINITECOMPLETIONS = TRUE. Maximum of 8 if INFINITECOMPLETIONS = FALSE.
VC0TOTALCREDITSPD
(((VC0RXFIFOLIMITP – VC0RXFIFOBASEP +1)× 8) – (VC0TOTALCREDITSPH × 24))/16
VC0TOTALCREDITSCD 0 if INFINITECOMPLETIONS = TRUE, otherwise (((VC0RXFIFOLIMITC –
VC0RXFIFOBASEC + 1) × 8) – (VC0TOTALCREDITSCH × 16))/16
INFINITECOMPLETIONS TRUE or FALSE