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92 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Appendix A: Integrated Endpoint Block Attributes

interspersed with smaller packets. Care should be taken in opting to specify a larger

number of packets than the FIFO technically has room for, to ensure that allowance has

been made for effects that ordering rules can have on the packets needing to be handled.

The other factor that needs to be considered is the absolute limit of eight packets that can

be handled by any FIFO.

Note:

The number of packets that the FIFO can handle determines the maximum number of flow

control credits that can be offered for any particular type of packet. The

TOTALCREDITS attributes are

used to initialize the flow control credits. More information on the setting of these attributes is given in

Table A-7, page 96.

Because the block RAM interface is 64 bits wide, the VC0FIFOBASE* and VC0FIFOLIMIT*

pointers should be defined accordingly. For example,

VC0TXFIFOBASEP will be set to 0, so

VC0TXFIFOLIMITP = [Posted TX FIFO size (in bytes)] / 8 - 1. More information on the buffer

sizing is given in “Block RAM Interface,” page 40.

Buffer Latency

Allowable buffer latency is established by setting the appropriate attributes, shown in

Table A-1.

• The

TLRAMREADLATENCY attribute applies to both TX and RX buffer READs.

• The

TLRAMWRITELATENCY attribute applies to both the TX and RX buffer WRITEs.

• The Retry buffer latencies (

RETRYRAMREADLATENCY and RETRYRAMWRITELATENCY)

can be controlled independently.

The read latency attribute settings are calculated as:

# block RAM output registers (0 or 1)

+ # of fabric read pipeline stages (data)

+ # of fabric read pipeline stages (address/control)

Read Latency Setting

Typical settings are given Table A-2. Other cases are possible, but probably not very useful.

For the purposes of this calculation,

TRUE = 1 and FALSE = 0.

Note:

The difference between the TLRAMREADLATENCY and RETRYRAMREADLATENCY

settings must be no more than two.

Tab le A -1 : Allowed RAM Latency Settings

Attribute Applicable Buffer(s) Allowed Latencies

TLRAMREADLATENCY

TX, RX 2 – 6

TLRAMWRITELATENCY

TX, RX 1 – 2

RETRYRAMREADLATENCY

Retry 2 – 6

RETRYRAMWRITELATENCY

Retry 1 – 2