User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 87
UG197 (v1.5) July 22, 2009
Known Restrictions
R
Receipt of Back-to-Back ACK DLLPs
Whenever ACKs are received in consecutive cycles for x8 designs, the TX path of the block
can lock up.
Workaround
Users can work around this issue by monitoring the interface between the integrated
Endpoint block and the RocketIO transceivers and nullify the second ACK by zeroing out
all the bits in the ACK DLLP.
This workaound is implemented in LogiCORE Endpoint Block Plus for PCI Express
Designs v1.8 or later. No workarounds are implemented in LogiCORE Endpoint Block for
PCI Express Designs.