User guide

86 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 4: Integrated Endpoint Block Operation

Credit Leak When Transmitting Completion TLPs

Whenever a minimum size completion TLP (1DW) entering the TX completion buffer

causes it to become full and there is a pending configuration completion at the same time,

then the configuration completion is incorrectly entered into the TX posted buffer. This

results in a reduction of advertised posted credits and no reduction in advertised

completion credits, which are both incorrect. This could potentially lead to two symptoms:

• A completion will be transmitted when the partner device does not have credits to

accept it causing flow control protocol error.

• Posted packets will be stalled even though the partner device has enough credits to

accept the packet.

Workaround

Users can perform flow control in the FPGA and prevent a minimum size completion from

being presented to the integrated Endpoint block, if it is in danger of causing the transmit

completion buffer to become full. This requires monitoring several statistics signals to

accurately measure the occupancy level of the transmit completion buffer. This

workaround is implemented in LogiCORE Endpoint Block Plus for PCI Express Designs

v1.6.1 or later. No workaround is implemented in LogiCORE Endpoint Block for PCI

Express Designs.

Receipt of Ignored Messages

Whenever an ignored message is received, the integrated Endpoint block does not perform

any action on it and the message is passed to the user logic.

Workaround

The user should monitor the user interface for receipt of an ignored message and perform

appropriate user action as per the PCI Express Base Specification 1.1, section 2.2.8.7.

No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE

Endpoint Block for PCI Express Designs.

Receipt of Unsupported Configuration Requests and Poisoned

Configuration Writes

Whenever an unsupported configuration request is received (for example, a configuration

request to functions 1 to 7) OR a poisoned configuration request is received, the integrated

Endpoint block incorrectly sets the correctable error detected and unsupported request

detected bits.

Workaround

The user should implement a separate version (set correctly) of the correctable error

detected and unsupported request detected bits in user logic. These registers should be

used to overwrite the internal bits when host reads the Device Control register and Status

This workaround is implemented in LogiCORE Endpoint Block Plus for PCI Express

Designs v1.3 or later. No workarounds are implemented in LogiCORE Endpoint Block for

PCI Express Designs.