User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 85
UG197 (v1.5) July 22, 2009
Known Restrictions
R
Workaround
The user can work around this issue by introducing a delay of 160 ns (equal to
40 CRMCORECLK cycles) in the FPGA logic on the
RXELECIDLE 0/1 signals in the interface
between the RocketIO transceiver and the integrated Endpoint block. The user can build a
single FPGA logic design that turns on the delay whenever
L0LTSSMSTATE = Loopback,
thus preventing delay during normal operation.
No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE
Endpoint Block for PCI Express Designs.
Link Upconfigure Bit on TS2 Training Sequence
The integrated Endpoint block is designed for forward compatibility with PCI Express
Base Specification 2.0 and successful interoperability. However, there is one exception.
According to the PCI Express Specification 2.0, a bit in the TS2 sequence is used as a Link
Upconfigure bit. This bit is reserved in the PCI Express Specification 1.1. The integrated
Endpoint block is expected to transmit a 1 on this bit and ignore the value on the RX side.
The integrated Endpoint block does not ignore this bit and fails to link train if it is set to 1.
Workaround
The user should force this bit to 0 in each lane by inserting FPGA logic in the interface
between the RocketIO transceiver and the integrated Endpoint block.
This workaround is implemented in LogiCORE Endpoint Block Plus for PCI Express
Designs v1.5 or later. No workarounds are implemented in LogiCORE Endpoint Block for
PCI Express Designs.
Returning to L1 from L0 in D3hot State
When an upstream component programs the integrated Endpoint block to the D3hot
power state, the integrated Endpoint block transitions into an L1 state. While the
integrated Endpoint block is in the D3hot state, if the upstream component sends a TLP,
then the block initiates entry into the L0 state in order to process the incoming TLP and
send completions, if necessary. After processing the TLP and sending any relevant
completions, the integrated Endpoint block does not return to the L1 state and remains in
the L0 state, which is not compliant.
Workaround
To avoid this scenario, the upstream component needs to initiate a D0 transition before
sending a TLP and initiate a D3hot transition after receiving any expected completions to
send the integrated Endpoint block back into the D3hot power state.
No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE
Endpoint Block for PCI Express Designs.