User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 83
UG197 (v1.5) July 22, 2009
Known Restrictions
R
Workaround
To avoid the issues listed, the user needs to prevent non-posted packets and completion
packets from being stalled inside the transmit buffer of the integrated Endpoint block. The
user needs to monitor the credit status through the management interface and send non-
posted and completion packets on the TLI only if sufficient credits are available for
transmission. The user determines if sufficient credits are available by monitoring “credits
consumed” and “credit limit” for non-posted and completion packets in the transmit
direction. The usage of the Management Interface ports for monitoring credit information
is described in Table 2-7, page 38.
No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE
Endpoint Block for PCI Express Designs.
REPLAY_NUM Rollover in LTSSM State TX.L0s
If a given packet is replayed several times, it causes REPLAY_NUM to rollover. According
to the PCI Express Base Specification 1.1, this should always trigger link training.
However, the integrated Endpoint block will not initiate link training due to
REPLAY_NUM rollover if the LTSSM state is TX.L0s. As a result, the block returns to the L0
state instead of the Recovery state, and will not replay any packets. The block will continue
to remain in this state until link training is initiated.
Workaround
To avoid this scenario, the user can inject TS1 training sets into the receive path of the block
when the LTSSM returns to the L0 state. Insert training sets by adding FPGA logic at the
Transceiver interface. Monitor signals
L0DLLERRVECTOR[3] and L0LTSSMSTATE to detect
when a rollover occurs and the state of the LTSSM.
No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE
Endpoint Block for PCI Express Designs.
ACK Ignored When Followed by IDLE Ordered Set
When the host sends an ACK followed by an IDLE ordered set to initiate L0s.Entry, the
integrated Endpoint block never sees the ACK and instead replays the packet. If this
scenario repeats multiple times, REPLAY_NUM rolls over, causing the block to initiate link
training.
Workaround
To avoid this scenario, the user can intercept the IDLE ordered set and delay it in the FPGA
logic by adding logic at the Transceiver interface.
No workarounds are implemented in LogiCORE Endpoint Block Plus or LogiCORE
Endpoint Block for PCI Express Designs.