User guide

78 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block

UG197 (v1.5) July 22, 2009

Chapter 4: Integrated Endpoint Block Operation

Known Restrictions

This section describes several restrictions and anomalies in the functionality of the

integrated Endpoint block for PCI Express® designs. Designers must understand each

restriction and the potential impact on their application. This chapter also clearly describes

the user action required to work around the restrictions and anomalies. In some cases there

are no workarounds available. Wherever applicable, the availability of the workaround in

the LogiCORE™ IP Endpoint Block Plus Wrapper is indicated. Designers must read the

descriptions and workarounds carefully before proceeding to design.

TX Transmission Issues Due to Lack of Data Credits

Whenever the transmission of a minimum size packet (1DW posted or completion, non-

posted) causes the transmit buffers to run out of data credits (while header credits are still

available), then one of the following symptoms can result in x8 designs:

• A nullified TLP is transmitted. This occurs when the transmit path incorrectly starts

transmission of a TLP when the buffer is empty and subsequently nullifies it.

• TLPs could be sent out of order. This will result in non-posted packets potentially

passing posted packets.

• A valid TLP is transmitted when there are no credits available. This could result in the

TLP being dropped by the partner device due to lack of buffer space to accept the TLP.

In addition, if the partner device is configured so that the advertised flow control credits

follow the guidelines shown in Table 4-6, the symptoms described in this section will not

occur. Completion packets need to satisfy one of the two guidelines (row 3 OR row 4 in

Table 4-6).

For Table 4-6, all credits are in units of four DWORDs = 16 bytes and

n = MPS/16 or MTU/16 (where the maximum payload size (MPS) and maximum

transfer unit (MTU) are expressed in bytes).

Workaround

The user can perform flow control in the FPGA and prevent a minimum size packet from

being presented to the integrated Endpoint block if it is in danger of running out of data

credits. This requires monitoring the advertised credit information, the consumed credit

information from the integrated Endpoint block, and the occupancy levels of the transmit

buffers. This workaround is implemented in LogiCORE Endpoint Block Plus for PCI

Express Designs v1.6.1 or later. This workaround has a potential performance impact of up

to 12% (worst case scenario). Actual numbers will vary across applications and systems,

and could be much lower. No workaround is implemented in LogiCORE Endpoint Block

for PCI Express Designs.

Table 4-6: Advertised Flow Control Credits Guidelines (from Partner Device)

Packet Type Header Credits Data Credits

Non Posted x 0 or ≥ x

Posted x ≥ x ∗ n

Completions 0 0

Completions x ≥ x ∗ n