User guide

68 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 4: Integrated Endpoint Block Operation
R
applied to determine which packet(s) can be legally read in accordance with the PCI
strongly ordered model:
• A posted packet can be read when
LLKRXCHPOSTEDAVAILABLEN is asserted, which
allows a posted packet to pass a non-posted or completion packet.
• A non-posted packet can be read when
LLKRXCHNONPOSTEDAVAILABLEN is asserted
and
LLKRXPREFERREDTYPE indicates the non-posted channel, which prevents a non-
posted packet from passing a posted or completion packet.
• A completion packet can be read when
LLKRXCHCOMPLETIONAVAILABLEN is asserted
and
LLKRXPREFERREDTYPE indicates completion.
• A completion packet can be read when
LLKRXCHCOMPLETIONAVAILABLEN is asserted
and
LLKRXCHPOSTEDAVAILABLEN is not asserted, which allows a completion packet
to pass a non-posted packet, but not a posted packet.
The user logic can choose to modify the completion rule when the relaxed ordering bit is
set on the packet. (If a request is made with the relaxed ordering bit set, the received
completion should have the relaxed ordering bit set.) In this case:
• A completion packet can be read when
LLKRXCHCOMPLETIONAVAILABLEN is asserted,
regardless of
LLKRXPREFERREDTYPE, which allows a completion packet to pass
either a non-posted packet or a posted packet.
When packets are available in more than one traffic class, the user can choose to service the
traffic classes in any order. For more information on PCI Express transaction ordering
rules, see section 2.4.1 of the PCI Express Base 1.1 Specification.
In certain cases, the ordering rules allows transactions of different types to be made known
to the user logic simultaneously. The PCI Express Base Specification states that in such cases,
it is up to the user logic to arbitrate between the different transaction type streams (though
it does recommend certain strategies).
As with transmission, transactions with the same type cannot be passed to the user out of
sequence because they are placed into the same received FIFO pipeline and therefore
cannot pass each other.
Performance Considerations
The user application should avoid situations where non-posted or completion packets are
stalled in the transmit buffers due to lack of flow control credits. Many systems advertise
infinite completions, so this is primarily an issue for non-posted packets. This can be
accomplished by monitoring the CREDIT_LIMIT and CREDIT_CONSUMED values in the
Management interface to ensure that there are sufficient credits before pushing a packet
through the Transaction Layer interface.
On the receive side, the user application should make sure packets are received through
the Transaction Layer interface as quickly as possible and that forward progress is always
made.
Interrupt Handling
The integrated Endpoint block supports sending interrupt requests as either Legacy
interrupts or Message Signaled Interrupts (MSI). The mode is programmed using the MSI
Enable bit in the Message Control register of the MSI Capability structure. If the MSI
Enable bit is set to 1, then the user application can generate MSI requests by creating and
sending memory write TLPs on the transmit Transaction Layer interface. If the MSI Enable
bit is reset to 0, the block generates Legacy interrupt messages as long as the Interrupt