User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 67
UG197 (v1.5) July 22, 2009
Transaction Ordering
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Transaction Ordering
The PCI Express Base Specification has rules about the type of traffic that can overtake other
types of traffic to avoid blockages.
The PCI Express ordering rules apply at transmission of Transaction Layer packets, and
also at reception and transfer through the Transaction Layer interface to the user
application. The details are given in “Ordering at Transmission,” page 67 and “Ordering at
Reception,” page 67.
Ordering at Transmission
The Transaction Layer arbitrates between each Transmit buffer to give each buffer access to
the Data Link Layer transmit logic, based upon the PCI Express ordering rules, which are
outlined in Table 4-1.
The integrated Endpoint block primarily chooses between the three transmit streams
based on how long the packets have been waiting. The general rule is that the oldest is sent
first. However, should there be a delay in processing a particular type of traffic (e.g., due to
a lack of flow control credits), then the block could allow packets of other traffic types to be
sent instead – based on the above ordering rules.
The integrated Endpoint block never allows two transactions of the same type to be
transmitted out of order, because both transactions are placed into the same FIFO pipeline
and it is impossible for one transaction to leapfrog another inside the same buffer.
Ordering at Reception
The LLKRXPREFERREDTYPE signals indicate a recommended packet type that could be
received in compliance with ordering rules, although there could be other packet types
that qualify to be received in compliance. The
LLKRXCH*AVAILABLEN signals indicate when
a packet is available in the RX buffer, but in some cases receiving the packet could violate
ordering rules.
The incoming stream of transactions is placed into the RX buffers, and each transaction
header is given an order code by the integrated Endpoint block as it is placed into the RX
posted, RX non-posted, or RX completion buffer.
The outputs provided to the user logic then become active in accordance with the ordering
rules. For example, if a posted request is waiting for processing and its order code is earlier
than a non-posted request also waiting in the receive buffers,
LLKRXPREFERREDTYPE
indicates the posted queue, while the
LLKRXCH*AVAILABLE signals indicate that packets are
available in both the posted and non-posted queues.
The
LLKRXPREFERREDTYPE and LLKRXCH*AVAILABLEN signals together indicate when
incoming packets are available and legal to receive according to the PCIe transaction
ordering rules. These signals have separate bits to indicate the preferred type and packet
availability for each traffic class. Within a given traffic class, the following rules must be
Table 4-1: Summary of Ordering Rules Applied: Can “Row” pass “Column?”
Posted Request Non-Posted Request Completion
Posted Request No Yes Yes
Non-Posted Request No No Yes
Completion No Yes No