User guide

66 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 4: Integrated Endpoint Block Operation
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has transmitted. Every time the TL transmits a packet, it increments the count of credits
consumed so far. When the transmitted data has exhausted the current credit limit held by
the transmitter (the last credit value to be received from the device at the other end of the
link), it halts transmission of new data of that type until it receives an UpdateFC packet.
The number of flow control credits that the integrated Endpoint block initially advertises
for each of the receive FIFOs must be set through various attributes, depending on how
much buffer space is allocated to the receiver. These attributes need to be set to record the
number of packets of the selected type that can be handled by the corresponding FIFO,
considering both the size of the FIFO and the overriding maximum of eight packets that
can be buffered by any FIFO. The initial flow control attribute values are automatically
calculated and set in the Endpoint Block Plus Wrapper. See Appendix A for more
information.
When working as the receiver, the integrated Endpoint block counts the number of credits
of each type consumed as it routes each incoming packet to the appropriate RX buffer. The
credit count is used for error checking since an overflow error will occur if the number of
credits consumed ever exceeds the number of credits advertised to the device at the other
end of the link. If this happens, the integrated Endpoint block flags the error to the
configuration block, which then sends an error message packet to the host.
Note:
The transmission of UpdateFC packets is monitored via a timer that is reset each time an
UpdateFC packet is sent. If this timer expires, transmission of new Transaction Layer packets is
halted in the Data Link Layer while the UpdateFC packet can be sent.
The four flow control registers detailed in the PCI Express Base Specification
(
CREDITS_CONSUMED, CREDIT_LIMIT, CREDITS_ALLOCATED, and the optional
CREDITS_RECEIVED) are all implemented by the integrated Endpoint block. The values of
these registers can be read using the
MGMTSTATSCREDITSEL and MGMTSTATSCREDIT
buses in the Management Interface.
Note:
The optional timeout mechanism detailed in Section 2.6.1.2 of the PCI Express Base
Specification is implemented inside the Transaction Layer.
Configuration Requests
Endpoints receive configuration request packets addressing their internal configuration
registers from the PCIe link.
Configuration read and write request packets are included in the traffic received by the
Transaction Layer from the Data Link Layer. Type 0 configuration requests are
automatically filtered out and passed to the integrated Endpoint block’s Configuration
and Capabilities module without any need for intervention from the user logic.
Responses from the Configuration and Capabilities module are automatically constructed
into Transaction Layer completion packets and placed in the TX completion buffer for
transmission back to the configuration requester over the PCIe link.
Completions for Configuration requests compete with User Application generated TLPs in
the Transmit direction. Configuration completions can be stalled if there is a continuous
stream of three to four DW TLPs being transmitted by the User Application. In such a
scenario, the user should ensure there are frequent gaps in transmission to allow
Configuration completions to be transmitted.