User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 53
UG197 (v1.5) July 22, 2009
Registers
R
Registers
The tables in this section describe the registers in the integrated Endpoint block. All
registers can be read through the Management interface, and those designated read/write
(RW) can also be written. Note that the addresses given in the following tables refer to the
Management interface address (
MGMTADDR[10:0]). The addresses used when accessing the
configuration registers through configuration read and write packets are different, and can
be found in the PCI-SIG specifications.
Legacy Configuration Registers (Type 0)
Further documentation on each of the registers in the following tables can be found in the
appropriate specifications on the PCI-SIG website (www.pcisig.com
). The registers are
read on MGMTRDATA[31:0] or written to MGMTWDATA[31:0].
Table 2-17: Legacy Configuration Registers
Management
Address (Hex)
MGMTADDR[10:0]
Register Name
(1)
Read Only or
Read Write
0 Device ID; Vendor ID RW; RW
1 Status; Command RO; RO
2 Class Code; Revision ID RW; RW
3 Header Type; Cache Line Size RO; RO
4 Base Address Registers (BAR0) RO
5 Base Address Registers (BAR1) RO
6 Base Address Registers (BAR2) RO
7 Base Address Registers (BAR3) RO
8 Base Address Registers (BAR4) RO
9 Base Address Registers (BAR5) RO
A Cardbus CIS Pointer RW
B Subsystem ID; Subsystem Vendor ID RW; RW
C Expansion ROM Base Address RO
D Interrupt Pin; Interrupt Line; Capabilities Pointer RW; RO; RW
E base_addr0_mask
(2)
RO
F base_addr1_mask
(2)
RO
10 rom_base_addr_mask RO
11 base_addr2_mask
(2)
RO
12 base_addr3_mask
(2)
RO
13 base_addr4_mask
(2)
RO
14 base_addr5_mask
(2)
RO
15 Reserved RO