User guide

52 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
BUSMASTERENABLE
Output user_clk Bus Master Enable. When 0, the
Endpoint is prevented from issuing
any memory or I/O requests.
PARITYERRORRESPONSE
Output user_clk Parity Error Response. When 1,
response to Master Data parity errors
has been enabled.
SERRENABLE
Output user_clk SERR Enable. When 1, reporting of
fatal and nonfatal errors has been
enabled.
INTERRUPTDISABLE
Output user_clk Interrupt Disable. When 1, device is
prevented from generating INTx
interrupt messages.
URREPORTINGENABLE
Output user_clk Unsupported request reporting enable.
When 1, reporting of unsupported
requests has been enabled.
AUXPOWER
Input user_clk Not supported. Must be tied Low.
DLLTXPMDLLPOUTSTANDING
Output core_clk Not used. Driven to 0.
L0UNLOCKRECEIVED
Output user_clk Not supported.
L0PACKETHEADERFROMUSER[127:0]
Input user_clk Not supported. Must be tied Low.
Table 2-16: Configuration and Status Ports (Continued)
Port Direction
Clock
Domain
Description