User guide

50 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
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L0SETCOMPLETIONTIMEOUTCORRERROR
Input user_clk Asserted to indicate that a requester
has not seen a completion and has
handled this as a Correctable Error.
Causes the relevant “Completion
Timeout” status bit(s) to be set to 1.
L0SETUNEXPECTEDCOMPLETIONUNCORRERROR
Input user_clk Asserted to indicate that a receiver has
received an unexpected completion
and has handled this as an
Uncorrectable Error. Causes the
relevant Unexpected Completion
status bit(s) to be set to 1.
L0SETUNEXPECTEDCOMPLETIONCORRERROR
Input user_clk Asserted to indicate that a receiver has
received an unexpected completion
and has handled this as a Correctable
Error. Causes the relevant Unexpected
Completion status bit(s) to be set to 1.
L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR
Input user_clk Asserted to indicate that a completer
has received an unsupported non-
posted request. Causes the relevant
unsupported request status bit(s) to be
set to 1.
L0SETUNSUPPORTEDREQUESTOTHERERROR
Input user_clk Asserted to indicate that a completer
has received some other kind of
unsupported request (other than a non-
posted request). Causes the relevant
unsupported request status bit(s) to be
set to 1.
L0LEGACYINTFUNCT0
Input user_clk Drive High to request Legacy Interrupt
on Function 0.
L0MSIREQUEST0[3:0]
Input user_clk Not supported. Must be tied Low.
L0MSIENABLE0
Output user_clk Asserted when MSI is enabled for
Function 0.
L0MULTIMSGEN0[2:0]
Output user_clk Asserted when MSI multiple messages
are enabled for Function 0.
L0STATSDLLPRECEIVED
Output core_clk Asserted for a single clock cycle when a
DLLP is received.
L0STATSDLLPTRANSMITTED
Output core_clk Asserted for a single clock cycle when a
DLLP is transmitted.
L0STATSOSRECEIVED
Output core_clk Asserted for a single clock cycle when
an ordered set is received.
L0STATSOSTRANSMITTED
Output core_clk Asserted for a single clock cycle when
an ordered set is transmitted.
L0STATSTLPRECEIVED
Output core_clk Asserted for a single clock cycle when a
TLP is received.
Table 2-16: Configuration and Status Ports (Continued)
Port Direction
Clock
Domain
Description