User guide

48 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Chapter 2: Integrated Endpoint Block Functionality
R
L0DLUPDOWN[7:0]
Output core_clk When operating as an Endpoint in a
PCIe design, a rising edge on this signal
flags the transition from the InitFC1
phase of the initialization procedure to
the InitFC2 phase. A falling edge
indicates that the link has been broken
and is used as a trigger for the link to be
reset. There is a bit for each
implemented VC.
Bits [7:1] are never used.
L0CFGDISABLESCRAMBLE
Input core_clk When asserted at power-up, disables
the MAC scrambler. Provided for use in
debugging communication issues
between linked devices after physical
connectivity has been confirmed using
loopback (see
L0CFGLOOPBACKMASTER).
L0DLLERRORVECTOR[6:0]
Output core_clk Error signals relating to DLL data.
Errors detected within the DLL result
in the relevant bit in the vector being
asserted for one clock period:
bit 0:
DLLBADTLP
bit 1: DLLBADDLLP
bit 2: DLLREPLAYTIMEOUT
bit 3: DLLREPLAYROLLOVER
bit 4: Reserved
bit 5:
RXTLPMISSING
bit 6: DLLPROTOCOLERROR
A missing TLP triggers both bit 5 and
bit 0.
The same error in consecutive DLLPs
results in the associated bit being
asserted for more than one clock period
where the DLLPs are presented back-
to-back to the Data Link Layer by the
MAC.
L0COMPLETERID[12:0]
Output user_clk Bus number and device number
components of the Completer ID.
Append the 3-bit Function number, 0,
to form the full 16-bit Completer ID.
Also used as the Requester ID for
Request TLPs.
L0TRANSACTIONSPENDING
Input user_clk Assert when there are outstanding
transactions pending. Setting reflected
in setting of the Transaction Pending
bit in the Device Status register.
Table 2-16: Configuration and Status Ports (Continued)
Port Direction
Clock
Domain
Description