User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 45
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
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Power Management Interface
This interface includes ports related to Power Management. Most ports in this interface are
tied off by the CORE Generator wrapper.
Table 2-15: Power Management Ports
Port Direction
Clock
Domain
Description
L0PWRSTATE0[1:0] Output user_clk Indicates the current device power state as follows:
00:D0
01:D1
10:D2
11:D3
(1)
Can be used to inhibit transfers while the block is in the D1
or D2 state.
L0PWRL1STATE
Output user_clk Asserted when the link is in the L1 power state.
L0PWRL23READYSTATE
Output user_clk Asserted when the link is in the L2/L3 power state.
L0PWRTXL0SSTATE
Output user_clk Asserted when TX Link is in the L0s power state.
L0PWRTURNOFFREQ
Output user_clk Asserted when port has received a PMETURNOFF
message. The integrated Endpoint block immediately
sends a PME_TO_Ack message in response. After this
signal is asserted, the user application is guaranteed power
for a minimum of 250 ns to prepare and do maintenance
tasks before the power is turned off. Afterwards, the power
can be turned off by the Root at any time.
L0MACNEWSTATEACK
Output core_clk Acknowledgment that the link has transitioned to the
requested new link power state.
L0MACRXL0SSTATE
Output core_clk Asserted when receiver has gone into the RxL0s state.
L0MACENTEREDL0
Output core_clk Pulsed when the MAC transitions back into the L0 link
power state.
L0PMEREQIN
Input core_clk Not supported. Must be tied Low.
L0PMEACK
Output user_clk Not supported.
L0PMEREQOUT
Output user_clk Not supported.
L0PMEEN
Output user_clk Not supported.
L0RXDLLPM
Output core_clk Not used. Driven to 0.
L0RXDLLPMTYPE[2:0]
Output core_clk Not used. Driven to 0.
L0DLLRXACKOUTSTANDING
Output core_clk Not used. Driven to 0.
L0DLLTXOUTSTANDING
Output core_clk Not used. Driven to 0.
L0DLLTXNONFCOUTSTANDING
Output core_clk Not used. Driven to 0.
Notes:
1. When an upstream component programs the integrated Endpoint block to the D3hot power state, the integrated Endpoint block
transitions into an L1 state. While the integrated Endpoint block is in the D3hot state, if the upstream component sends a TLP, then
the block initiates entry into the L0 state in order to process the incoming TLP and send completions, if necessary. After processing
the TLP and sending any relevant completions, the integrated Endpoint block does not return to the L1 state and remains in the L0
state, which is not compliant. To avoid this scenario, the upstream component needs to initiate a D0 transition before sending a TLP
and initiate a D3hot transition after receiving any expected completions to send the integrated Endpoint block back into the D3hot
power state.