User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 43
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
RocketIO transceiver ports in each GTP_DUAL or GTX_DUAL tile. The 0/1 designation is
omitted from Table 2-14 for simplicity.
For multilane designs, lane 0 should be connected to the RocketIO transceiver channel
bonding master.
Table 2-14: RocketIO Transceiver Interface Ports
Port Direction
Clock
Domain
Description
PIPERXELECIDLELn
Input core_clk Electrical idle detected on receive channel of selected
lane. Connect to the
RXELECIDLE port on the RocketIO
transceiver or tie High for unused lanes.
PIPERXSTATUSLn[2:0]
Input core_clk Encodes receiver status and error codes for the received
data stream and receiver detection on selected lane.
000: Data received OK
001: One skip symbol (SKP) added
010: One SKP removed
011: Receiver detected
100: 8B/10B decode error
101: Elastic Buffer overflow
110: Elastic Buffer underflow
111: Receive disparity error
Connect to the
RXSTATUS[2:0] ports on the RocketIO
transceiver or tie Low for unused lanes.
PIPERXDATALn[7:0]
Input core_clk Receive data. Connect to the RXDATA[7:0] ports on the
RocketIO transceiver or tie Low for unused lanes.
PIPERXDATAKLn
Input core_clk Control bit(s) for receive data.
0: Data byte
1: Control byte
Connect to the
RXCHARISK[0] port on the RocketIO
transceiver or tie Low for unused lanes.
PIPEPHYSTATUSLn
Input core_clk Communicates completion of RocketIO transceiver
functions like power management, state transitions, and
receiver detection on lane. For state transitions between
P0, P0s, and P1, the RocketIO transceiver indicates a
successful transition by a single cycle assertion of
PIPEPHYSTATUSLn. Connect to the PHYSTATUS port on
the RocketIO transceiver or tie Low for unused lanes.
PIPERXVALIDLn
Input core_clk Symbol lock and valid data on
PIPERXDATALn and
PIPERXDATAKLn. Connect to the RXVALID port on the
RocketIO transceiver or tie Low for unused lanes.
PIPERXCHANISALIGNEDLn
Input core_clk Signal from the RocketIO transceiver elastic buffer. Stays
High to denote that the channel is properly aligned with
the master transceiver according to observed channel
bonding sequences in the data stream. Connect to the
RXCHANISALIGNED port on the RocketIO transceiver or
tie Low for unused lanes.
PIPETXDATALn[7:0]
Output core_clk Transmit data for selected lane. Connect to the
TXDATA[7:0] ports on the RocketIO transceiver.