User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 41
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
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A pipeline stage can be added in the fabric between the integrated Endpoint and block
RAM blocks, if necessary, to meet timing. A pipeline stage can be added for either read or
write, or both. It is possible to pipeline address/control or data or both. See “Buffer
Latency” in Appendix A for more information. These additional pipeline stages are not
automatically added in the CORE Generator wrapper because whether or not they are
needed depends on the placement of the rest of the user's design.
RX and TX Buffer Capacity
Although the TX, RX, and Retry buffers are implemented using fully configurable block
RAM, there are hard limits on how many packets can be buffered in the TX and RX buffers.
Table 2-9 shows the maximum number of packets that can be buffered for each of the RX
and TX buffers. The number of packets that can be buffered can be further limited by the
various FIFO sizes and the negotiated maximum payload size set when the link is
initialized.
The size of posted or completion packets is the size of the payload plus the size of the
header. The posted header size should be 24 bytes, due to rounding up because of the
64-bit buffer width; 16 bytes should be used for the completion header size. Non-posted
packets should be allocated 24 bytes each, due to rounding up.
Retry Buffer Size
The optimal size of the Retry buffer depends on the level of traffic that is expected, because
the buffer needs to be large enough not to throttle the traffic flow. At a minimum, the buffer
should be able to hold at least two TLPs of the size exchanged between the integrated
Endpoint block and the device to which it is attached (the negotiated maximum payload
size set when the link is initialized). See Table 2-10.
The minimum size can be calculated by using the
XPMAXPAYLOAD attribute (128, 256, 512,
1024, 2048, or 4096 bytes), and adding overhead for sequence number, redundancy checks,
and header information. The overhead is 16 bytes for PCIe packets without ECRC. For
example, if
XPMAXPAYLOAD is 2048 bytes and ECRC is not used, the minimum Retry buffer
size is 2 × (2048 + 16) = 4128 bytes. The calculated value is then rounded up to the next
available Retry buffer size, which is 8192 bytes in this example.
Table 2-9: Maximum RX and TX Buffer Capacity
Maximum Number
of Packets (VC0)
Maximum Size
(VC0)
Posted Packets 8 32 Kbytes
Non-Posted Packets 8 512 bytes
Completion Packets 8 32 Kbytes
Table 2-10: Recommended Minimum Retry Buffer Sizes
XPMAXPAYLOAD
Minimum Retry Buffer Size
128 4096 bytes
256 4096 bytes
512 4096 bytes
1024 4096 bytes
2048 8192 bytes
4096 16384 bytes