User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 39
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
MGMTSTATSCREDIT[11:0]
Output user_clk Credit information as selected by
MGMTSTATSCREDITSEL[6:0]. MGMTSTATSCREDIT[11:0] is
updated two cycles after MGMTSTATSCREDITSEL[6:0] is
switched.
MGMTSTATSCREDITSEL[6:0]
Input user_clk Channel select for credit information output to
MGMTSTATSCREDIT[11:0].
Bits [1:0] select VC0:
00:VC0
01: Reserved
10: Reserved
11: Reserved
Bits [4:2] select the channel.
000:Posted header (PH)
001: Non-posted header (NPH)
010: Completion header (CH)
011: Posted data (PD)
100: Non-posted data (NPD)
101: Completion data (CD)
110: Reserved
111: Reserved
Bits [6:5] select the type of credit information.
00: credits consumed - TX credits used by transmitted
packets
01: credit limit - TX credits received from link partner
10: credits allocated - RX credits issued to link partner
11: credits received - RX credits consumed by received
packets
MGMTPSO[16]
Output user_clk Master Data parity error. Bit 8 of the Status register.
MGMTPSO[15]
Output user_clk Signaled Target abort. Bit 11 of the Status register.
MGMTPSO[14]
Output user_clk Received Target abort. Bit 12 of the Status register.
MGMTPSO[13]
Output user_clk Received Master abort. Bit 13 of the Status register.
MGMTPSO[12]
Output user_clk Signaled system error. Bit 14 of the Status register.
MGMTPSO[11]
Output user_clk Detected parity error (poisoned TLP). Bit 15 of the Status
register.
MGMTPSO[10]
Output user_clk Correctable error detected. Bit 0 of the Device Status register.
MGMTPSO[9]
Output user_clk Nonfatal error detected. Bit 1 of the Device Status register.
MGMTPSO[8]
Output user_clk Fatal error detected. Bit 2 of the Device Status register.
MGMTPSO[7]
Output user_clk Unsupported request detected. Bit 3 of the Device Status
register.
MGMTPSO[6]
Output user_clk Transactions Pending. Bit 5 of the Device Status register.
MGMTPSO[5:0]
Output user_clk Reserved.
Table 2-7: Management Interface Ports (Continued)
Port Direction
Clock
Domain
Description