User guide

Virtex-5 FPGA Integrated Endpoint Block www.xilinx.com 35
UG197 (v1.5) July 22, 2009
Virtex-5 FPGA Integrated Endpoint Block Interface Descriptions
R
LLKTXCHANSPACE[9:0]
Output user_clk Amount of free space in the TX FIFO as selected by
LLKTXCHTC and LLKTXCHFIFO.
Bit [9] indicates if space is available for header:
1: Space for one header
0: No space for header
Bit [8] indicates if space is available for data:
1: Space for data
0: No space for data
Bits [7:0] indicate the number of data credits
available:
1 .. 255: Number of credits available
0: Meaning depends on bit [8] setting:
– If bit [8] = 0, no credits are available.
– If bit [8] = 1, at least 256 credits are available.
LLKTXSOFN
Input user_clk Transaction Layer interface TX Start of Frame (active
Low).
LLKTXEOFN
Input user_clk Transaction Layer interface TX End of Frame (active
Low).
LLKTXSOPN
Input user_clk Not supported. Must be tied High.
LLKTXEOPN
Input user_clk Not supported. Must be tied High.
LLKTXENABLEN[1:0]
Input user_clk Word enable for Transaction Layer interface
Transmit bus (active Low).
LLKTXCHTC[2:0]
Input user_clk Traffic class portion of Channel Select.
LLKTXCHFIFO[1:0]
Input user_clk FIFO portion of Channel Select.
00:Posted
01: Non-posted
10:Completion
11: Reserved
LLKTXCHPOSTEDREADYN[7:0]
Output user_clk Channel ready for posted packets TC7 – TC0 (active
Low).
LLKTXCHNONPOSTEDREADYN[7:0]
Output user_clk Channel ready for non-posted packets TC7 – TC0
(active Low).
LLKTXCHCOMPLETIONREADYN[7:0]
Output user_clk Channel ready for completion packets TC7 – TC0
(active Low).
LLKRXDATA[63:0]
Output user_clk Transaction Layer interface receive data.
Table 2-6: Transaction Layer Interface Ports (Continued)
Port Direction
Clock
Domain
Description